DCS dCS 974, Digital to Digital Converter SPDIF Message Handling

dCS 974 User Manual	Manual for Software Version 1.0x
dCS Ltd	May 2001

SPDIF Message Handling

The SPDIF interface (sometimes known as the Consumer AES/EBU interface) transmits a data structure that conforms to the IEC 95826 standard. Like the AES/EBU, this contains 28 bits of Manchester encoded data, and a 4 bit near- Manchester encoded preamble in a subframe, and subframes are further assembled in a block and frame structure. The difference lies only in the voltage levels, and the Channel Status bits (the System Message). It contains 24 bits of audio data.

IMPORTANT! The AES/EBU interface and the SPDIF interface have similar data structures, although the messages are completely different. The two structures are identified in the data domain by the use of the Consumer/Professional bit (bit 1 in the message). A "1" indicates AES/EBU format, a "0" indicates SPDIF format.

The default SPDIF message attached to the output data by the unit before being changed by the user is as follows:

Professional:	Off
Non-Audio:	Off
Copy Permit:	On
Format:	2-Channel General Format

26See EN 60958:1995 or IEC 958:1989 with amendments 1&2. The structure of the message is sufficiently complex that it is best to read the source material.

Manual part no: DOC1241121A1

Page 89

Document No: OS-MA-A0124-112.1A1

Contact dCS on + 44 1799 531 999	email to: more@dcsltd.co.uk
(inside the UK replace + 44 with 0)	web site: www.dcsltd.co.uk

Contents

© 2001 dCS Ltd dCS Ltd PRODUCT OVERVIEW Monitoring Test Generator Ease of Use About this Manual About Sample Rates CONTENTS The Hardware – Controls and Connectors Page Page STEP-BY-STEP GUIDE Preliminaries Step 1 – Selecting an Input Connecting to a Dual AES Source Connecting to a Quad AES source Connecting to a DSD SDIF-2source WCLK IN Connecting to a DSD Quad source Step 2 – Setting the Sync Source Syncing to an AES/EBU Reference AES Ref Loop Step 3 - Setting a Conversion proceed to Setting the Output Mode Setting the Output Sample Rate Setting the Output mode Step 4 – Connecting the Outputs Step 5 – Reducing the Output Wordlength Proceed to Other Settings Other Settings Sample Rate Conversion / Format Conversion Submenu TYPICAL APPLICATIONS Converting a 24/96 recording to CD format Demultiplexing a 24/96 Dual AES recording (Bit for Bit) Upsampling a CD General Sample Rate Conversion and Distribution PCM to DSD Using a Master Clock Converting Quad AES to CD Format Multi-channelSample Rate Conversion – bit aligned sources Multi-channelSample Rate Conversion – Using a Master Clock Multi-channelSample Rate Conversion – with more alignment tolerance Multi-channelSample Rate Conversion – with multiple sample rates out Page THE SOFTWARE – MENU AND SETUPS Page Navigating through the Menu – what the On-Screensymbols mean Page Top Menu Error Monitoring Test Info Bit Activity Monitors NOT Level Meters Display Sample Rate Conversion / Format Conversion Submenu Multiple Channel Sync Multiple Channel Sync’ing Single Master Slave Input Sample Rate Output Sample Rate 1 pass INPUT SAMPLE RATE (kS/s) OUTPUT SAMPLE RATE (kS/s) 2 Pass Output Mode AES Clk Output SDIF Clk Output dCS 974 Performance Curves Out Number of Filters Available Output Word Length Noise Shaping AES Message Edit SPDIF Message Edit Gain/Balance and Maximise not Swap Channels L/R Flip Phase Detect Silence De/Pre-Emphasis Display Customise Page Error Monitor Submenu Test Submenu Generator Amplitude Adjustment Generator Frequency Adjustment Self Test Info Submenu Bit Activity Monitor Submenu Level Meters Submenu Meter Type (Bar or Numerical) Decay Time Set Using the dCS 974 to monitor a track Watch Out for this One Display Submenu Setups and Locking the Front Panel Demo “First choose a name!” AES2 DSD DSDQ Fixed Setups AES1 Au>24 DA Au>CD N9 F2 QA Au>CD N9 F2 DSD2>CD N9 F2 Locking Out Changes, and Unlocking Again Error Monitor Bit Activity Monitor Level Meter Page THE HARDWARE – CONTROLS AND CONNECTORS Rear Panel Signal Outputs AES/EBU Digital Outputs 3 pin XLR Male (4 off – AES 1, AES 2, AES 3, AES 4) AES 2, AES AES/EBU Clock Output3 pin XLR Male (1 off – AES CLK OUT) Front Panel LED indicators Noise shaping L/R flip Gain Balance Digital Data Formats Supported DSD E2 spec E3 spec DSD Data Formats PCM Input and/or Output Performance Spurs Noise Group Delay Group Delay (∝s) Sample Period (∝s) Conversion Clocking Sample Alignment SDIF WCLK IN Page Page Multiple Channel Sync’ing Page Multiple Channel Multiple Sample Rate Synchronising Noise Shaping Dither Digital Interface Specifications SPDIF (optical) Message Handling SPDIF Message Handling SDIF-2Message Handling DESCRIPTION Definition Default Message Power Consumption Size, Weight and Operating Conditions Page dCS 974 PERFORMANCE CURVES Page Page Page Page Page Page Page Page Page GENERAL TECHNICAL INFORMATION Word Length Reduction lower Truncation Type, with Noise 44.1 kS/s data rate unweighted What does it look like Page When is Dither Needed Page USING YOUR dCS 974 FOR THE FIRST TIME What’s in the Box Supply Voltage Setting Getting Started Page Installing the Unit in a Rack Page OPTIONS Locking to Video Sample Rates Mains Supply Voltage Ordering Options for a New Unit Having Your Options Changed Page MAINTENANCE AND SUPPORT Hardware Software Warranty Update or Calibration Safety and Electrical Safety TROUBLESHOOTING FAQs Page “Invalid Fs Out for Fs In” message The Customise Display menu will not allow another option to be set If You Need More Help Other Information INDEXES AND SOFTWARE VERSION NUMBERS Definitions of Units Tables Figures Keywords and Phrases Page Page Page Page Owner Registration Transfer