DCS dCS 974, Digital to Digital Converter Multiple Channel Sync’ing, input, input, input, sample, Time in, 96 kS/s, 44.1 kS/s, Time in ns, Time in ns, rate UI’s20, as in Figure, AES CLK Output

dCS 974 User Manual	Manual for Software Version 1.0x
dCS Ltd	May 2001

Multiple Channel Sync’ing

Multiple channel sync’ing requires more things to be in sync than two channel work - the PLL must not be dual modulus, the DSP algorithm must load with a constant group delay, and the frame and block syncs must agree.

The dCS 974 meets all these constraints with the addition of a syncing signal transmitted from a master unit to subsequent slave units. To do this, it passes information in the User Bits of the AES3 message. To slave adequately, units must have this sync information input to the AES Ref Loop Input, via a sync link. Each slave will generate a copy, based on its own timing, for transmission to the next unit in the chain. If the Multi-channel Sync option is set to On in the Sample Rate Conversion menu, any units with no user bit synchronisation data into its AES Ref Loop Input will become a Master. If user bit synchronisation information is fed in, it will become a slave. Either unit will output synchronisation information via its AES CLK Output. A master clock (dCS 992 19) can be used as the master – if more than about 8 channels are being used, this system is best, as it avoids any tolerance build up. Connections are shown in the multi-channel syncing applications, starting on page 29.

Using the multi-channel sync mode, the timing of the data at the output of the dCS 974 is related to the data coming in. If three dCS 974 units are used in a six channel set up, and the data into all of them is bit sync’d from (say) a six channel source, the outputs will be bit sync’d. If the inputs are not quite bit aligned, then the outputs will not quite be bit aligned. If the inputs are way off in phase but frequency locked, the outputs will be way off in phase but frequency locked, and the timing of the block structures of the several output signals will not be defined.

Sample Rate (kS/s)					Time in	Time in ns,	Time in ns,
					input	44.1 kS/s	96 kS/s
					sample	input	input
					rate UI’s20
Basic dCS	974	unit	to	unit	± 0.3	± 50	± 24
output timing alignment.
Input misalignment			allowed,		± 2	± 334	± 162
with all inputs at the same
frequency,		for	block
structuring	to	work		(no
Master Clock).
Input misalignment			allowed,		± 4	± 668	± 324
with all inputs at the same
frequency, with Master Clock
Input misalignment			allowed,		± 64	± 11338	± 5208
with all inputs at the same
frequency, with Master Clock
as in Figure 1621.

Table 8 – Multiple Channel Sync mode – allowable input misalignment

The scope shots below show the timing relationships between two units, using the sync link, for various conversions. They are taken from 2 units, with scope probes on the same point in each unit. The units are linked by a sync link.

19version 2.0 software or higher.

20UI = Unit Interval, see AES3 spec. There are 128 UI’s per sample in AES3.

21Master Clock can adjust its Wordclock phases as necessary.

Manual part no: DOC1241121A1 Page 81 Document No: OS-MA-A0124-112.1A1

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