Ta b l e 4 - 7 . P E R C 3 / S C

S p e c i f i c a t i o n s (continued)

 

 

Parameter

Specification

 

 

SCSI controller

One SCSI controller for 160M and Wide support

 

 

SCSI data transfer rate

Up to 160 MB/s per channel

 

 

SCSI bus

Low-voltage differential (LVD) or single-ended

 

 

SCSI termination

Active

 

 

Termination disable

Automatic through cable and device detection

 

 

Devices per SCSI channel

Up to 15 wide or seven narrow SCSI devices

 

 

SCSI device types

Synchronous or asynchronous

 

 

RAID levels supported

0, 1, 5, 10, and 50

 

 

SCSI connectors

One 68-pin internal high-density connectors for

 

16-bit SCSI devices. One ultra-high density 68-

 

pin external connectors for 160M and Wide

 

SCSI.

 

 

Serial port

3-pin RS232C-compatible connector (for

 

manufacturing use only)

 

 

PCI Bridge/CPU

PERC 3/SC uses the Intel i960RM PCI bridge with an embedded i960RM RISC processor running at 100 MHz. The RM bridge handles data transfers between the primary (host) PCI bus, the secondary PCI bus, cache memory, and the SCSI bus. The DMA controller supports chaining and unaligned data transfers. The embedded i960JT CPU directs all controller functions, including command processing, SCSI bus transfers, RAID processing, drive rebuilding, cache management, and error recovery.

Cache Memory

32 MB of PERC 3/SC cache memory resides in a memory bank. PERC 3/SC supports write-through or write-back caching, selectable for each logical drive. To improve performance in sequential disk accesses, the PERC 3/SC controller uses read-ahead caching by default. You can disable read-ahead caching.

PERC 3/SC Features

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Dell 3 manual PCI Bridge/CPU, Cache Memory