CC1000dm Request/Grant Local PCI Bus Device | Emerson CC1000DM

Table 3-5:

Request/Grant Assignments

	P M C / P C I I N T E R F A C E	.
	P M C / P C I I N T E R F A C E	.
	PMC Module Installation	.
	PMC Module Installation	.
		.
		. .

to…

1001 PCI 6254 has highest priority

1010-1111 reserved

BPC: Bus Parking Control

This controls the bus grant behavior during idle. 0000 Last master granted is parked (default) 0001 Master #0 is parked

to…

1001 Master #8 is parked

1010 PCI 6254 is parked Others Grant is deasserted

The secondary arbiter implements a programmable two-level rotating algorithm whereby the priorities are re-evaluated at the start of each new transaction on the sec- ondary PCI bus. From this point until the time the next transactions starts, the arbiter will assert grants corresponding to the highest priority request asserted. The arbiter sup- ports up to ten request/grant pairs. The request/grant assignments for the arbiter are shown in the following table. For more detailed information regarding arbitration, refer to the PLX PCI 6254 documentation listed in the Technical References Table 1-2.

CC1000dm
Request/Grant		Local PCI Bus Device:
0		PMC 1



1		PMC 2

2		reserved

3		reserved

4		PMC 1 Alternate Device

5		PMC 2 Alternate Device

6		reserved

7		reserved

8		reserved

9		PCI 6254

10004281-02

CC1000dm User’s Manual 3-5

Image 37

Emerson CC1000DM user manual CC1000dm Request/Grant Local PCI Bus Device

Contents

CC1000dm Revision Level Principal Changes Date Regulatory Agency Warnings & Notices EC Declaration of Conformity Contents Bridge Eeprom PCI Bridge Features PMC Module Installation Figures G u r e s Tables Ta b l e s Registers G i s t e r s Overview Functional Overview N. .C.T.I.O. N. .A. L. . O. .V.E. R. .V.I.E.W Product Certification Type SpecificationRoHS Compliance Technical References Terminology and NotationAdditional Information Device / Interface Document Document 6CC1000dm User’s Manual 10004281-02 Width Depth Setup Component Map, Top rev CC1000dm Circuit Board CC1000dm Circuit Board Identification Numbers Connectors Fuses and Jumpers Jumper/Header Locations, Top View Multiple Option Selection JP3 CC1000dm Setup Signal Name Bit Selection CC1000dm Setup Pin Signal Signal NameBit Selection Jumper Jumper Position ModeSel Environmental Considerations Power RequirementsOperational Checks Typical Current Voltage Range Amps S. E. .T. .M. E. .T.H. O. .D.S Non-transparent Reset Methods O. U. .B. L. E. .S.H. O. .O. T. I. N. .G Troubleshooting 14CC1000dm User’s Manual 10004281-02 PMC/PCI Interface Device Mapping PMC Module InstallationC / P C I I N T E R F a C E Volts Timing Interrupts Base cPCI Interrupt Transparent Mode Assignment SecondaryBase PCI Interrupt System controller modes Internal Arbiter Control Register CC1000dm Request/Grant Local PCI Bus Device Bridge Eeprom I.D. G. .E. .E.E. P. .R.O. M PCI 6254 Configuration Registers Power Management CSR PCI 6254 Configuration Registers 38h Reserved Status PCI Identification Values PCI 6254 Bridge ModeVendor Device Subsystem ID hex I. .B.U. S. . C. .O. N. .T.R. O. .L. .S.I.G. N. .A.L. S PCI Bus Control Signals PCI Bus Control Signals Pin J11 J12 J13 J14 PMC Connector Pin Assignments J13 J14 Pin J11 J12 Pin J11Pin J21 J23 J24 Pin J21 J22 Pin J21 J22 J23 J24 Carrier Card BUS Interface Arbitration and Device Selection O. C. .K. .G. E. .N. E. R. .A.T. I.O. .N Model Description Hot Swap Hot Swap Implementation Signal Description CC1000dm Control SignalsPin Row Z Row a Row B Row C Row D Row E Row F Pin Row Z Row a Row B Row C Row D Row E Backplane Connector Pin Assignments Pin Row a Row B Row C Row D Row E Row F Row F Pin Row a Row B Row C Row D Row E Backplane Connector Pin Assignments 10CC1000dm User’s Manual 10004281-02 PrPMC CPCI O s s a r y Index D e Page W. a r t e s y n c p . c o m