2
Figure
PLD Signal
S E T U P
Reset Methods
| Transparent |
PCI_VIO | PCI_VIO |
| 5.11 K | 10 K |
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| 5.11 K | 10 K |
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| PMC_RSTOUT* |
| PMC_RSTOUT* | |||||
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| PLD |
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| PCIXCAP_HEALTHY* | PLD |
| |
| PCIXCAP_HEALTHY* | BRIDGE_RST* |
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| (internal signal) |
| BRIDGE_RST* | |
CONN_CPCI_RST 10 | (internal signal) |
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| CONN_CPCI_RST 10 |
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CPCI_RST* |
| BRIDGE_RST_OUT* | CPCI_RST* |
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| BRIDGE_RST_OUT* | ||
CONN_CPCI_BD_SEL* |
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| S_RSTIN* | CONN_CPCI_BD_SEL* |
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| (1) | S_RSTIN* |
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| S_RSTOUT* |
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| S_RSTOUT* | ||
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BACKSIDE_PWR_GD |
| HSON* | PWRGD*HS |
| BACKSIDE_PWR_GD |
| HSON* | PWRGD*HS |
BACKSIDE_PWR_RST* |
| BACKSIDE_PWR_RST* | ||||||
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Legacy | No System Controller |
PCI_VIO | PCI_VIO |
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| 5.11 K | 10 K |
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| 5.11 K | 10 K |
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| PMC_RSTOUT* |
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| PMC_RSTOUT* | |||
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| |||
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| PLD |
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| PLD |
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| BRIDGE_RST* |
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| BRIDGE_RST* | |
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CONN_CPCI_RST 10 | CPCI_RST* |
| BRIDGE_RST_OUT* | CONN_CPCI_RST 10 | CPCI_RST* |
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| BRIDGE_RST_OUT* |
CONN_CPCI_BD_SEL* |
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| S_RSTIN* | CONN_CPCI_BD_SEL* |
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| S_RSTIN* |
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| S_RSTOUT* |
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| S_RSTOUT* | ||
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| (0) |
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BACKSIDE_PWR_GD |
| HSON* | PWRGD*HS |
| BACKSIDE_PWR_GD |
| HSON* | PWRGD*HS |
BACKSIDE_PWR_RST* |
| BACKSIDE_PWR_RST* | ||||||
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Any of the following methods reset the entire board:
•At
•The voltage monitor detects voltage supplies of +5 V, +3.3 V, +12
•Input from the cPCI reset signal (except when in the no system controller mode)
•Pressing the reset switch (SW1) on the CC1000dm front panel
•Writing to the PLX PCI 6254 (HB6) Bridge Control register from the PCI address space can generate a reset on the
•Input from the RSTOUT* signal from either PMC slot 1 or PMC slot 2.