Epson S1C62 Family BR, BRR, BR, BRR SET/RESET BREAK REGISTER CONDITION, 1:, 0:, -:C, -:1, -:0, #BR, Y030:, Format, ---:040, ---:041, ---:030, Function, X041:042, Examples #BR

ICE CONTROL SOFTWARE ICS62XX

BR, BRR SET/RESET BREAK REGISTER CONDITION

Format #BR (With guidance)

#BRR

Function A break condition is set in the evaluation board CPU registers A, B, FLAG, X (Xp, Xh, Xl,) or Y (Yp, Yh, Yl).

(1) BR: A break condition is set in the target registers A, B, FLAG, X (Xp, Xh, Xl,) or Y (Yp, Yh, Yl). The break condition in each register can be masked (a masked register can generate a break in another register, whatever the specified value). Break is induced when the values of each register correspond to the set values in the internal CPU registers.

(2)BRR: Cancels a break condition set by BR command.

(3)A break set by the BR command is operative at one point. BA and BD settings can be mixed.

(4)A BR condition can be canceled by executing the BM command.

Examples #BR			... A hyphen (-) is displayed when a BR condition is not set
	A	-:C
	B	-:*	Break condition is sequentially set
	FI	-:1	... Enter an asterisk (*) mark to indicate masking
	FD	-:*
	FZ	-:0	This induces a break unrelated to the FD value
	FC	-:*
	X	---:040	... If a parameter is mis-set, entering the ^ key will return
	Y	---:^
	X	---:041	the operation to the previous setting (one less than the
	Y	---:030	current setting)

A break condition set as described above, where A=C, FI=1, FZ=0, X=41, and Y=30.

#BR

A	C:	... Reads a previously set break condition
B	*:	When no setting modification is made, hitting the	key
FI	1:*	continues the operation to the next setting
FD	*:
FZ	0:*
FC	*:

X041:042Y030:*

Two break conditions where A=C and X=42 are described above.

VIII-54	EPSON	S1C62 FAMILY
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