ICE CONTROL SOFTWARE ICS62XX

2.3.3SYNC pin and HALT pin output

(1)SYNC Pin Output

When the instruction cycle conforms to a break condition, a low level pulse is output by the first half of the subsequent instruction fetch cycle.

Evaluation board clock

Fetch signal

Instruction cycle

SYNC output

5 clock instruction

Correspond to break condition

Fig. 2.3.3.1 SYNC pin output

About 1 ∝ sec (clock 455 kHz) About 15.6 ∝ sec (clock 32 kHz)

(2)HALT Pin Output

A low level pulse is output when the evaluation board CPU is stopped (e.g., when the HALT or SLP instructions are executed).

HALT output

Fig. 2.3.3.2 HALT pin output

Indicate the CPU halt

2.3.4Display during run mode and during break

During run mode, the ICE control processor monitors the state of the evaluation board CPU. Monitored data evaluation board CPU's executed program are displayed at intervals of about 500 msec when the on- the-fly display mode is set (by the OTF command).

#G

*PC=0120 . . . Underlined portion is displayed in succession. *PC=HALT . . . Enter HALT mode, line feed, and HALT is displayed. *PC=0200 . . . HALT is canceled, operation is restarted, and PC is redisplayed.

Note HALT indicates execution of the HALT or SLP instruction.

When the printer is online and started, the PC values are printed in succession. PC is not displayed during on-the-fly inhibit mode.

During a break, the cause of the break, post break PC (the next executed program address), the contents of the CPU registers, and execution time are displayed.

#G

 

 

 

 

 

 

 

*PC=xxxx

. . . (1)

*EMULATION END STATUS=BREAK HIT

*PC=0201 A=0 B=0 X=070 Y=071 F=IDZC SP=10

. . . (2)

*RUN TIME=425.097mS

. . . (3)

(1)There are three statuses possible after completing the emulation: BREAK HIT, ESC KEY, OR BREAK SW. When a number of conditions prevail, only the highest priority position is displayed in the follow- ing priority ranking: BREAK SW > ESC KEY > BREAK HIT. A break may also be initiated by the reset switch; a reset switch break causes " *ICE6200 RESET SW TARGET* " to be displayed and instructions are awaited. The register display and execution time display are not active in this mode.

(2)The displayed PC shows the next executed value. Register values following "A" indicate the values during a break. In the above example, the values (indicated 2) results from completing to execute the instruction of address 0200.

VIII-12

EPSON

S1C62 FAMILY

 

 

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