CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

4.11.9 I/O memory of serial interface

Tables 4.11.9.1(a) and (b) show the serial interface control bits and their addresses.

Table 4.11.9.1(a) Serial interface control bits

Address

 

Register

 

 

 

 

 

 

 

 

 

 

Comment

 

 

 

D3

D2

D1

D0

Name

Init ∗ 1

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PUL13

1

On

Off

 

P13 pull-up control register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

General-purpose register when SIF (clock sync. slave) is selected

 

 

PUL13

PUL12

PUL11

PUL10

PUL12

1

On

Off

 

P12 pull-up control register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

General-purpose register when SIF (clock sync. master) is selected

FF45H

 

 

 

 

 

 

 

 

 

SCLK (I) pull-up control register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

when SIF (clock sync. slave) is selected

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PUL11

1

On

Off

 

P11 pull-up control register (ESIF=0)

 

 

 

 

 

 

R/W

 

 

 

 

 

 

General-purpose register when SIF is selected

 

 

 

 

 

 

 

 

 

PUL10

1

On

Off

 

P10 pull-up control register (ESIF=0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SIN pull-up control register when SIF is selected

 

 

 

 

 

 

 

 

PUL33

1

On

Off

 

P33 pull-up control register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

General-purpose register when SIF (clock sync. slave) is selected

 

 

PUL33

PUL32

PUL31

PUL30

PUL32

1

On

Off

 

P32 pull-up control register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

General-purpose register when SIF (clock sync. master) is selected

 

 

 

 

 

 

 

 

 

 

 

 

 

(I) pull-up control register

 

 

 

 

FF4DH

 

 

 

 

 

 

 

 

 

SCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

when SIF (clock sync. slave) is selected

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PUL31

1

On

Off

 

P31 pull-up control register (ESIFS=0)

 

 

 

 

 

 

R/W

 

 

 

 

 

 

General-purpose register when SIF is selected

 

 

 

 

 

 

 

 

 

PUL30

1

On

Off

 

P30 pull-up control register (ESIFS=0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SIN pull-up control register when SIF is selected

 

 

 

 

0

SMD1S

SMD0S

ESIFS

0 ∗ 3

– ∗ 2

 

 

 

Unused

[SMD1S, 0S]

0

1

 

 

FF58H

SMD1S

0

 

 

 

 

Serial I/F (2)

Mode

Clk-sync. master

Clk-sync. slave

 

 

 

 

 

 

 

 

 

[SMD1S, 0S]

2

3

 

 

 

 

 

 

SMD0S

0

 

 

 

 

mode selection

 

 

 

 

R

 

R/W

 

 

 

 

 

Mode

Async. 7-bit

Async. 8-bit

 

 

 

 

 

 

 

 

 

 

 

 

 

ESIFS

0

SIF

I/O

 

Serial I/F (2) enable (P3x port function selection)

 

 

 

 

 

 

 

 

 

 

 

 

 

EPRS

PMDS

SCS1S

SCS0S

EPRS

0

Enable

Disable

 

Serial I/F (2) parity enable register

 

 

 

 

 

 

PMDS

0

Odd

Even

 

Serial I/F (2) parity mode selection

 

 

 

 

FF59H

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

SCS1S

0

 

 

 

 

SIF (2) clock

[SCS1S, 0S] 0

1

2

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCS0S

0

 

 

 

 

source selection Mode

1200bps 600bps 2400bps

PT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RXTRGS

0

Run

Stop

 

Serial I/F (2) receive status (reading)

 

 

 

 

 

 

RXTRGS

RXENS

TXTRGS

TXENS

 

 

Trigger

–

 

Serial I/F (2) receive trigger (writing)

 

 

 

FF5AH

 

 

 

 

 

RXENS

0

Enable

Disable

 

Serial I/F (2) receive enable

 

 

 

 

 

 

 

 

 

 

TXTRGS

0

Run

Stop

 

Serial I/F (2) transmit status (reading)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

Trigger

–

 

Serial I/F (2) transmit trigger (writing)

 

 

 

 

 

 

 

 

 

TXENS

0

Enable

Disable

 

Serial I/F (2) transmit enable

 

 

 

 

 

 

 

 

 

 

 

0 ∗ 3

– ∗ 2

 

 

 

Unused

 

 

 

 

 

 

 

 

 

0

FERS

PERS

OERS

FERS

0

Error

No error

 

Serial I/F (2) framing error flag status (reading)

 

 

 

 

 

 

 

Reset

–

 

Serial I/F (2) framing error flag reset (writing)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FF5BH

 

 

 

 

PERS

0

Error

No error

 

Serial I/F (2) parity error flag status (reading)

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

R/W

 

 

 

Reset

–

 

Serial I/F (2) parity error flag reset (writing)

 

 

 

 

 

 

 

OERS

0

Error

No error

 

Serial I/F (2) overrun error flag status (reading)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

–

 

Serial I/F (2) overrun error flag reset (writing)

 

 

 

 

 

TRXD3S

TRXD2S

TRXD1S

TRXD0S

TRXD3S

– ∗ 2

High

Low

 

 

 

 

 

 

 

 

 

 

 

FF5CH

 

TRXD2S

– ∗ 2

High

Low

 

 

Serial I/F (2) transmit/receive data (low-order 4 bits)

 

 

 

 

R/W

 

TRXD1S

– ∗ 2

High

Low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRXD0S

– ∗ 2

High

Low

 

 

LSB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRXD7S

TRXD6S

TRXD5S

TRXD4S

TRXD7S

– ∗ 2

High

Low

 

 

MSB

 

 

 

 

 

 

 

FF5DH

 

TRXD6S

– ∗ 2

High

Low

 

 

Serial I/F (2) transmit/receive data (high-order 4 bits)

 

 

 

 

R/W

 

TRXD5S

– ∗ 2

High

Low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRXD4S

– ∗ 2

High

Low

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*1 Initial value at initial reset

*2 Not set in the circuit

*3 Constantly "0" when being read

92

EPSON

S1C63558 TECHNICAL MANUAL