CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)

In an asynchronous system, RXTRG is used to prepare for next data receiving. After reading the received data from the receive data buffer, write "1" into RXTRG to signify that the receive data buffer is empty. If "1" is not written into RXTRG, the overrun error flag OER will be set to "1" when the next receiving operation is completed. (An overrun error will be generated when receiving is completed between reading the received data and the writing of "1" to RXTRG.)

In addition, RXTRG can be read as a status bit. In either clock synchronous mode or asynchronous mode, when RXTRG is set to "1", it indicates receiving operation and when set to "0", it indicates that receiving has stopped.

For details on timing, see the timing chart which gives the timing for each mode.

When you do not receive, set RXEN to "0" to disable receiving.

4.11.6 Operation of clock synchronous transfer

Clock synchronous transfer involves the transfer of 8-bit data by synchronizing it to eight clocks. The same synchronous clock is used by both the transmitting and receiving sides.

When the serial interface is used in the master mode, the clock signal selected using SCS0 and SCS1 is further divided by 1/16 and employed as the synchronous clock. This signal is then sent via the SCLK terminal to the slave side (external serial I/O device).

When used in the slave mode, the clock input to the SCLK terminal from the master side (external serial input/output device) is used as the synchronous clock.

In the clock synchronous mode, since one clock line (SCLK) is shared for both transmitting and receiving, transmitting and receiving cannot be performed simultaneously. (Half duplex only is possible in clock synchronous mode.)

Transfer data is fixed at 8 bits and both transmitting and receiving are conducted with the LSB (bit 0) coming first.

SCLK

 

 

 

LSB

MSB

Data

D0 D1 D2 D3 D4 D5 D6 D7

Fig. 4.11.6.1 Transfer data configuration using clock synchronous mode

Below is a description of initialization when performing clock synchronous transfer, transmit-receive control procedures and operations.

With respect to serial interface interrupt, see "4.11.8 Interrupt function".

Initialization of serial interface

When performing clock synchronous transfer, the following initial settings must be made.

(1)Setting of transmitting/receiving disable

To set the serial interface into a status in which both transmitting and receiving are disabled, "0" must be written to both the transmit enable register TXEN and the receive enable register RXEN. Fix these two registers to a disable status until data transfer actually begins.

(2)Port selection

Because serial interface input/output ports SIN, SOUT, SCLK and SRDY are set as I/O port terminals P10–P13 at initial reset, "1" must be written to the serial interface enable register ESIF in order to set these terminals for serial interface use.

(3)Setting of transfer mode

Select the clock synchronous mode by writing the data as indicated below to the two bits of the mode selection registers SMD0 and SMD1.

Master mode: SMD0 = "0", SMD1 = "0"

Slave mode: SMD0 = "1", SMD1 = "0"

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S1C63558 TECHNICAL MANUAL