CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)

Table 4.6.6.1(b) Control bits of I/O ports

Address

 

Register

 

 

 

 

 

 

 

 

 

Comment

 

 

D3

D2

D1

D0

Name

Init ∗1

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOC33

0

Output

Input

 

P33 I/O control register

 

 

 

 

 

 

IOC33

IOC32

IOC31

IOC30

 

 

 

 

 

General-purpose register when SIF (clock sync. slave) is selected

 

 

IOC32

0

Output

Input

 

P32 I/O control register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FF4CH

 

 

 

 

 

 

 

 

 

 

General-purpose register when SIF (clock sync.) is selected

 

 

 

 

 

IOC31

0

Output

Input

 

P31 I/O control register (ESIFS=0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

General-purpose register when SIF is selected

 

 

 

 

 

 

IOC30

0

Output

Input

 

P30 I/O control register (ESIFS=0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

General-purpose register when SIF is selected

 

 

 

 

 

 

 

 

PUL33

1

On

Off

 

P33 pull-up control register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

General-purpose register when SIF (clock sync. slave) is selected

 

 

PUL33

PUL32

PUL31

PUL30

PUL32

1

On

Off

 

P32 pull-up control register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

General-purpose register when SIF (clock sync. master) is selected

 

 

 

 

 

 

 

 

 

 

 

 

(I) pull-up control register

 

 

 

FF4DH

 

 

 

 

 

 

 

 

 

 

SCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

when SIF (clock sync. slave) is selected

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PUL31

1

On

Off

 

P31 pull-up control register (ESIFS=0)

 

 

 

 

 

R/W

 

 

 

 

 

 

General-purpose register when SIF is selected

 

 

 

 

 

 

 

 

PUL30

1

On

Off

 

P30 pull-up control register (ESIFS=0)

 

 

 

 

 

 

 

 

 

 

 

 

 

SIN pull-up control register when SIF is selected

 

 

 

 

 

 

P33

– ∗2

High

Low

 

P33 I/O port data

 

 

 

 

 

 

 

P33

P32

P31

P30

 

 

 

 

 

General-purpose register when SIF (clock sync. slave) is selected

 

 

(XSRDYS)

(XSCLKS)

(SOUTS)

(SINS)

P32

– ∗2

High

Low

 

P32 I/O port data

 

 

 

 

 

FF4EH

 

 

 

 

 

 

 

 

 

 

General-purpose register when SIF (clock sync.) is selected

 

 

 

 

 

P31

– ∗2

High

Low

 

P31 I/O port data (ESIFS=0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

General-purpose register when SIF is selected

 

 

 

 

 

 

P30

– ∗2

High

Low

 

P30 I/O port data (ESIFS=0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

General-purpose register when SIF is selected

 

 

 

 

0

SMD1S

SMD0S

ESIFS

0 ∗3

– ∗2

 

 

 

Unused

[SMD1S, 0S]

0

1

 

FF58H

SMD1S

0

 

 

 

 

Serial I/F (2)

Mode

Clk-sync. master

Clk-sync. slave

 

 

 

 

 

 

 

 

 

[SMD1S, 0S]

2

3

 

 

 

 

 

SMD0S

0

 

 

 

 

mode selection

 

 

 

R

 

R/W

 

 

 

 

 

Mode

Async. 7-bit

Async. 8-bit

 

 

 

 

 

 

 

 

 

 

 

 

 

ESIFS

0

SIF

I/O

 

Serial I/F (2) enable (P3x port function selection)

 

 

 

 

 

 

 

 

 

EXLCDC

ALOFF

ALON

LPAGE

EXLCDC

0

Enable

Disable

 

Expanded LCD driver signal control

 

 

 

 

 

ALOFF

1

All Off

Normal

 

LCD all Off control

 

 

 

 

FF61H

 

 

 

 

 

ALON

0

All On

Normal

 

LCD all On control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

 

LPAGE

0

F100-F15F

F000-F05F

 

Display memory area selection (when 1/8 duty is selected)

 

 

 

 

 

 

 

 

 

General-purpose register when 1/16, 1/17 duty is selected

 

 

 

 

 

 

 

 

 

 

 

 

 

0

SMD1

SMD0

ESIF

0 ∗3

– ∗2

 

 

 

Unused

[SMD1, 0]

0

1

 

FF70H

SMD1

0

 

 

 

 

Serial I/F (1)

Mode

Clk-sync. master

Clk-sync. slave

 

 

 

 

 

 

 

 

 

[SMD1, 0]

2

3

 

 

 

 

 

SMD0

0

 

 

 

 

mode selection

 

 

 

R

 

R/W

 

 

 

 

 

Mode

Async. 7-bit

Async. 8-bit

 

 

 

 

 

 

 

 

 

 

 

 

 

ESIF

0

SIF

I/O

 

Serial I/F (1) enable (P1x port function selection)

 

 

 

 

 

 

 

*1 Initial value at initial reset

*2 Not set in the circuit

*3 Constantly "0" when being read

(1) Selection of port functionEXLCDC: Expanded LCD driver signal control register (FF61H•D3)Sets P22 and P23 to the CL signal and the FR signal output ports.When "1" is written: CL/FR signal outputWhen "0" is written: I/O port

Reading: Valid

When setting P22 to the CL (LCD synchronous signal) output and P23 to the FR (LCD frame signal) output, write "1" to this register and when they are used as I/O ports, write "0".

The CL and FR signals are output from the P22 terminal and P23 terminal immediately after the functions are switched by the EXLCDC register. In this case, the control registers for P22 and P23 can be used as general purpose registers that do not affect the output.

At initial reset, this register is set to "0".

S1C63558 TECHNICAL MANUAL

EPSON

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