CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Timer)

4.9.4 I/O memory of stopwatch timer

Table 4.9.4.1 shows the I/O addresses and the control bits for the stopwatch timer.

 

 

 

 

 

 

 

Table 4.9.4.1

Control bits of stopwatch timer

Address

 

 

Register

 

 

 

 

 

 

 

 

Comment

D3

 

D2

 

D1

D0

Name

Init 1

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

SWRST

SWRUN

0 3

2

 

 

 

 

Unused

 

 

 

 

0 3

2

 

 

 

 

Unused

FF7CH

 

 

 

 

 

 

 

 

 

 

R

 

 

W

R/W

SWRST3

Reset

 

Reset

Invalid

 

Stopwatch timer reset (writing)

 

 

 

 

 

 

 

 

 

 

SWRUN

0

 

Run

Stop

 

Stopwatch timer Run/Stop

 

 

 

 

 

 

 

 

 

 

 

 

SWD3

 

SWD2

 

SWD1

SWD0

SWD3

0

 

 

 

 

 

 

 

 

 

 

SWD2

0

 

 

 

 

 

Stopwatch timer data

FF7DH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

SWD1

0

 

 

 

 

 

BCD (1/100 sec)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SWD0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SWD7

 

SWD6

 

SWD5

SWD4

SWD7

0

 

 

 

 

 

 

 

 

 

 

SWD6

0

 

 

 

 

 

Stopwatch timer data

FF7EH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

SWD5

0

 

 

 

 

 

BCD (1/10 sec)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SWD4

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

EISW1

EISW10

0 3

2

 

 

 

 

Unused

 

 

 

 

0 3

2

 

 

 

 

Unused

FFE7H

 

 

 

 

 

 

 

 

 

 

R

 

 

R/W

EISW1

0

 

Enable

Mask

 

Interrupt mask register (Stopwatch timer 1 Hz)

 

 

 

 

 

 

 

 

 

 

EISW10

0

 

Enable

Mask

 

Interrupt mask register (Stopwatch timer 10 Hz)

 

 

 

 

 

 

 

 

 

 

 

 

0

 

0

 

ISW1

ISW10

0 3

2

 

(R)

(R)

 

Unused

 

 

 

 

0 3

2

 

Yes

No

 

Unused

FFF7H

 

 

 

 

 

 

 

 

R

 

 

R/W

ISW1

0

 

(W)

(W)

 

Interrupt factor flag (Stopwatch timer 1 Hz)

 

 

 

 

 

 

 

 

 

 

ISW10

0

 

Reset

Invalid

 

Interrupt factor flag (Stopwatch timer 10 Hz)

 

 

 

 

 

 

 

 

 

 

*1 Initial value at initial reset

*2 Not set in the circuit

*3 Constantly "0" when being read

SWD0–SWD7: Stopwatch timer data (FF7DH, FF7EH)

The 1/100 sec and the 1/10 sec data (BCD) can be read from SWD0–SWD3 and SWD4–SWD7, respec- tively. These eight bits are read only, and writing operations are invalid.

At initial reset, the timer data is initialized to "00H".

SWRST: Stopwatch timer reset (FF7CH•D1)

When "1" is written: Stopwatch timer reset

When "0" is written: No operation

Reading: Always "0"

The stopwatch timer is reset by writing "1" to SWRST. All timer data is set to "0". When the stopwatch timer is reset in the RUN status, operation restarts immediately. Also, in the STOP status the reset data is maintained. No operation results when "0" is written to SWRST.

This bit is write-only, and so is always "0" at reading.

SWRUN: Stopwatch timer RUN/STOP control register (FF7CH•D0)

Controls RUN/STOP of the stopwatch timer.

When "1" is written: RUN

When "0" is written: STOP

Reading: Valid

The stopwatch timer enters the RUN status when "1" is written to the SWRUN register, and the STOP status when "0" is written.

In the STOP status, the timer data is maintained until the next RUN status or the timer is reset. Also, when the STOP status changes to the RUN status, the data that is maintained can be used for resuming the count.

S1C63558 TECHNICAL MANUAL

EPSON

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