Epson S1C63558 4.4.3 Mask option, Input port, (Initial value), Interrupt generation, Input comparison register, Interrupt selection register

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports)

The interrupt selection register (SIK) and input comparison register (KCP) are individually set for the input ports K00–K03 and K10–K13, and can specify the terminals for generating interrupt and interrupt timing.

The interrupt selection registers (SIK00–SIK03, SIK10–SIK13) select what input of K00–K03 and K10–K13 to use for the interrupt. Writing "1" into an interrupt selection register incorporates that input port into the interrupt generation conditions. The changing the input port where the interrupt selection register has been set to "0" does not affect the generation of the interrupt.

The input interrupt timing can select that the interrupt be generated at the rising edge of the input or that it be generated at the falling edge according to the set value of the input comparison registers (KCP00– KCP03, KCP10–KCP13).

By setting these two conditions, the interrupt for K00–K03 or K10–K13 is generated when input ports in which an interrupt has been enabled by the input selection registers and the contents of the input comparison registers have been changed from matching to no matching.

The interrupt mask registers (EIK0, EIK1) enable the interrupt mask to be selected for K00–K03 and K10– K13.

When the interrupt is generated, the interrupt factor flag (IK0, IK1) is set to "1". Figure 4.4.2.2 shows an example of an interrupt for K00–K03.

Interrupt selection register

SIK03	SIK02	SIK01	SIK00
1	1	1	0

Input comparison register

KCP03 KCP02 KCP01 KCP00

1 0 1 0

With the above setting, the interrupt of K00–K03 is generated under the following condition:

Input port

(1)	K03	K02	K01	K00
	1	0	1	0	(Initial value)
(2)
	K03	K02	K01	K00
	1	0	1	1
(3)
	K03	K02	K01	K00
	0	0	1	1		Interrupt generation
						Because K00 interrupt is set to disable, interrupt will be
(4)						generated when no matching occurs between the
	K03	K02	K01	K00
						contents of the 3 bits K01–K03 and the 3 bits input
	0	1	1	1		comparison register KCP01–KCP03.

Fig. 4.4.2.2 Example of interrupt of K00–K03

K00 interrupt is disabled by the interrupt selection register (SIK00), so that an interrupt does not occur at

(2). At (3), K03 changes to "0"; the data of the terminals that are interrupt enabled no longer match the data of the input comparison registers, so that interrupt occurs. As already explained, the condition for the interrupt to occur is the change in the port data and contents of the input comparison registers from matching to no matching. Hence, in (4), when the no matching status changes to another no matching status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect the conditions for interrupt generation.

4.4.3 Mask option

Internal pull-up resistor can be selected for each of the eight bits of the input ports (K00–K03, K10–K13) with the input port mask option.

When "Gate direct" is selected, take care that the floating status does not occur for the input. Select "With pull-up resistor" for input ports that are not being used.

S1C63558 TECHNICAL MANUAL EPSON 29