CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT)

4.16.2 Interrupt mask

The interrupt factor flags can be masked by the corresponding interrupt mask registers.

The interrupt mask registers are read/write registers. They are enabled (interrupt authorized) when "1" is written to them, and masked (interrupt inhibited) when "0" is written to them.

At initial reset, the interrupt mask register is set to "0".

Table 4.16.2.1 shows the correspondence between interrupt mask registers and interrupt factor flags.

Table 4.16.2.1 Interrupt mask registers and interrupt factor flags

Interrupt mask register

Interrupt factor flag

EID

(FFE9H•D0)

ID

(FFF9H•D0)

 

 

 

 

EIRDET

(FFEAH•D1)

IRDET

(FFFAH•D1)

EICDET

(FFEAH•D0)

ICDET

(FFFAH•D0)

 

 

 

 

EIPT1

(FFE2H•D1)

IPT1

(FFF2H•D1)

EIPT0

(FFE2H•D0)

IPT0

(FFF2H•D0)

 

 

 

 

EISER

(FFE3H•D2)

ISER

(FFF3H•D2)

EISRC

(FFE3H•D0)

ISRC

(FFF3H•D0)

EISTR

(FFE3H•D1)

ISTR

(FFF3H•D1)

EISERS

(FFE8H•D2)

ISERS

(FFF8H•D2)

EISRCS

(FFE8H•D0)

ISRCS

(FFF8H•D0)

EISTRS

(FFE8H•D1)

ISTRS

(FFF8H•D1)

 

 

 

 

EIK0

(FFE4H•D0)

IK0

(FFF4H•D0)

EIK1

(FFE5H•D0)

IK1

(FFF5H•D0)

 

 

 

 

EIT3

(FFE 6H•D3)

IT3

(FFF6H•D3)

EIT2

(FFE6H•D2)

IT2

(FFF6H•D2)

EIT1

(FFE6H•D1)

IT1

(FFF6H•D1)

EIT0

(FFE6H•D0)

IT0

(FFF6H•D0)

 

 

 

 

EISW1

(FFE7H•D1)

ISW1

(FFF7H•D1)

EISW10

(FFE7H•D0)

ISW10

(FFF7H•D0)

 

 

 

 

4.16.3 Interrupt vector

When an interrupt request is input to the CPU, the CPU begins interrupt processing. After the program being executed is terminated, the interrupt processing is executed in the following order.

1The content of the flag register is evacuated, then the I flag is reset.

2The address data (value of program counter) of the program to be executed next is saved in the stack area (RAM).

3The interrupt request causes the value of the interrupt vector (0100H–010EH) to be set in the program counter.

4The program at the specified address is executed (execution of interrupt processing routine by software).

Table 4.16.3.1 shows the correspondence of interrupt requests and interrupt vectors.

Table 4.16.3.1 Interrupt request and interrupt vectors

Interrupt vector

Interrupt factor

Priority

0100H

Watchdog timer

High

 

 

 

 

0102H

Dialer, FSK

 

 

 

 

 

 

 

 

0104H

Programmable timer

 

 

 

 

 

 

0106H

Serial interface (1), (2)

 

 

 

 

 

 

0108H

K00–K03 input

 

 

 

 

 

 

010AH

K10–K13 input

 

 

 

 

 

 

010CH

Clock timer

 

 

 

 

 

010EH

Stopwatch timer

Low

 

 

 

 

The four low-order bits of the program counter are indirectly addressed through the interrupt request.

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S1C63558 TECHNICAL MANUAL