CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (FSK Demodulator)

CDET: Carrier detection bit (FF66H•D0)

Indicates the carrier detection status.

When "1" is read: Carrier is detected

When "0" is read: Carrier is not detected

Writing: Invalid

CDET goes "1" when a carrier is input. When the carrier is stopped, CDET returns to "0". This bit is dedicated for reading, so writing can not be done.

At initial reset, this bit is set to "0".

RDETCP: RDET comparison register (FF67H•D1)

Sets a generation condition for the ring detection interrupt.

When "1" is written: RDET falling edge

When "0" is written: RDET rising edge

Reading: Valid

When RDETCP is set to "1", the ring detection interrupt is generated at the falling edge of the RDET signal. When RDETCP is "0", the interrupt is generated at the rising edge.

At initial reset, this register is set to "0".

CDETCP: CDET comparison register (FF67H•D0)

Sets a generation condition for the carrier detection interrupt.

When "1" is written: CDET falling edge

When "0" is written: CDET rising edge

Reading: Valid

When CDETCP is set to "1", the carrier detection interrupt is generated at the falling edge of the CDET signal. When CDETCP is "0", the interrupt is generated at the rising edge.

At initial reset, this register is set to "0".

EIRDET, EICDET: Interrupt mask registers (FFEAH•D1, D0)

Enables or disables the generation of an interrupt for the CPU.

When "1" is written: Enabled

When "0" is written: Disabled

Reading: Valid

EIRDET and EICDET are interrupt mask registers that respectively correspond to the interrupt factors for ring detection and carrier detection. Interrupts set to "1" are enabled and interrupts set to "0" are disabled. At initial reset, these registers are set to "0".

IRDET, ICDET: Interrupt factor flags (FFFAH•D1, D0)

Indicates the FSK interrupt generation status.

When "1" is read: Interrupt has occurred

When "0" is read: Interrupt has not occurred

When "1" is written: Flag is reset

When "0" is written: Invalid

IRDET and ICDET are interrupt factor flags that respectively correspond to the interrupts for ring detection and carrier detection, and are set to "1" by generation of each factor.

When set in this manner, if the corresponding interrupt enable mask is set to "1" and the CPU is set to interrupt enabled status (I flag = "1"), an interrupt will be generated to the CPU.

Regardless of the interrupt mask register setting, the interrupt factor flag will be set to "1" by the occurrence of an interrupt generation condition.

S1C63558 TECHNICAL MANUAL

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