Page
NOTICE
© SEIKO EPSON CORPORATION 2001, All rights reserved
SEIKO EPSON CORPORATION
Page
Page
The information of the product number change
Configuration of product number
Devices
S1 C 63158 F 0A01
Packing specification
Page
OUTLINE
Features
Block Diagram
Pin Layout Diagram
Pin Description
4.6 I/O Ports (P00–P03, P10–P13, P20–P23and P30–P33)
4.7 LCD Driver (COM0–COM16, SEG0–SEG39)
Clock Timer
Stopwatch Timer
4.10 Programmable Timer
SUMMARY OF NOTES
5.1 Notes for Low Current Consumption
5.2 Summary of Notes by Function
Precautions on Mounting
BASIC EXTERNAL WIRING DIAGRAM
CHAPTER 8 PACKAGE
Plastic Package
Ceramic Package for Test Samples
CHAPTER 9 PAD LAYOUT
Diagram of Pad Layout
CHAPTER 1 OUTLINE
1.1 Features
1.2 Block Diagram
1.3 Pin Layout Diagram
1.4 Pin Description
1.5 Mask Option
(8)Output specification of the DP terminal
(9)Gain of FSK demodulator input amplifier
(10)Output specification of other special output terminals
<Mask option list
1.MULTIPLE KEY ENTRY RESET COMBINATION
5. I/O PORT OUTPUT SPECIFICATION
6. I/O PORT PULL UP RESISTOR
7. DP PORT OUTPUT SPECIFICATION
8.SVD EXTERNAL VOLTAGE DETECTION
9.LCD DRIVER SPECIFICATION
2.1 Power Supply
2.1.1 Voltage <VD1> for oscillation circuit and internal circuits
2.1.2 Voltage <VC1–VC5>for LCD driving
2.2 Initial Reset
2.2.1 Reset terminal (RESET)
2.2.2 Simultaneous low input to terminals K00–K03
2.2.3 Internal register at initial resetting
2.2.4 Terminal settings at initial resetting
2.3 Test Terminal (TEST)
CHAPTER 3 CPU, ROM, RAM
3.1 CPU
3.2 Code ROM
3.3 RAM
3.4 Data ROM
CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION
4.1 Memory Map
Table 4.1.1 (a) I/O memory map (FF00H–FF18H)
Remarks
∗ 1 Initial value at initial reset
Constantly "0" when being read
∗ 2 Not set in the circuit
Table 4.1.1 (b) I/O memory map (FF20H–FF42H)
Table 4.1.1 (c) I/O memory map (FF44H–FF4DH)
Table 4.1.1 (d) I/O memory map (FF4EH–FF67H)
Table 4.1.1 (e) I/O memory map (FF6CH–FF7AH)
ransmit/receive data
Table 4.1.1 (f) I/O memory map (FF7CH–FFCBH)
Table 4.1.1 (g) I/O memory map (FFE2H–FFF7H)
Table 4.1.1 (h) I/O memory map (FFF8H–FFFAH)
4.2 Watchdog Timer
4.2.1 Configuration of watchdog timer
4.2.2 Interrupt function
4.2.3 I/O memory of watchdog timer
4.2.4 Programming notes
4.3 Oscillation Circuit
4.3.1 Configuration of oscillation circuit
4.3.2 OSC1 oscillation circuit
4.3.3 OSC3 oscillation circuit
4.3.4 Switching the CPU operating clock
4.3.5 Clock frequency and instruction execution time
4.3.6 I/O memory of oscillation circuit
4.3.7 Programming notes
4.4 Input Ports (K00–K03and K10–K13)
4.4.1 Configuration of input ports
4.4.2 Interrupt function
4.4.3 Mask option
4.4.4 I/O memory of input ports
SIK00–SIK03:K0 port interrupt selection register (FF20H)
SIK10–SIK13:K1 port interrupt selection register (FF24H)
KCP00–KCP03:K0 port input comparison register (FF22H)
KCP10–KCP13:K1 port input comparison register (FF26H)
EIK0: K0 input interrupt mask register (FFE4H•D0)
4.4.5 Programming notes
Output Ports
4.5.1 Configuration of output ports
4.5.2 Mask option
4.5.3 High impedance control
4.5.4 Special output
•XBZ (R00)
•BZ (R01)
•TOUT (R02)
•FOUT (R03)
•XTMUTE (R10)
•XRMUTE (R11)
•HDO (R12)
•HFO (R13)
4.5.5 I/O memory of output ports
R00HIZ–R03HIZ:R0 port high impedance control register (FF30H)
R10HIZ–R13HIZ:R1 port high impedance control register (FF32H)
R20HIZ–R23HIZ:R2 port high impedance control register (FF34H)
R00–R03:R0 output port data register (FF31H)
R10–R13:R1 output port data register (FF33H)
PTOUT: TOUT output control register (FFC1H•D2)
FOUTE: FOUT output control register (FF06H•D3)
FOFQ0, FOFQ1: FOUT frequency selection register (FF06H•D0, D1)
CTMO: R10 output selection register (FF13H•D0)
4.5.6 Programming notes
4.6 I/O Ports (P00–P03, P10–P13, P20–P23and P30–P33)
4.6.1 Configuration of I/O ports
4.6.2 Mask option
4.6.3 I/O control registers and input/output mode
4.6.4 Pull-upduring input mode
4.6.5 Special outputs (CL, FR)
4.6.6 I/O memory of I/O ports
Table 4.6.6.1(b) Control bits of I/O ports
(1) Selection of port function
EXLCDC: Expanded LCD driver signal control register (FF61H•D3)
Sets P22 and P23 to the CL signal and the FR signal output ports
When "1" is written: CL/FR signal output
ESIF: Serial interface (1) enable register (FF70H•D0)
ESIFS: Serial interface (2) enable register (FF58H•D0)
(2) I/O port control
P00–P03:P0 I/O port data register (FF42H)
P10–P13:P1 I/O port data register (FF46H)
IOC00–IOC03:P0 port I/O control register (FF40H)
IOC10–IOC13:P1 port I/O control register (FF44H)
IOC20–IOC23:P2 port I/O control register (FF48H)
IOC30–IOC33:P3 port I/O control register (FF4CH)
PUL00–PUL03:P0 port pull-upcontrol register (FF41H)
4.6.7 Programming notes
4.7 LCD Driver (COM0–COM16, SEG0–SEG39)
4.7.1 Configuration of LCD driver
4.7.2 Mask option
4.7.3 Power supply for LCD driving
4.7.4 LCD display control (ON/OFF) and switching of duty
(2)Switching of drive duty
4.7.5 Display memory
Page
4.7.6 LCD contrast adjustment
4.7.7 I/O memory of LCD driver
LPWR: LCD power control (ON/OFF) register (FF60H•D0)
LDUTY0, LDUTY1: LCD drive duty switching register (FF60H•D2, D3)
ALON: LCD all ON control register (FF61H•D1)
ALOFF: LCD all OFF control register (FF61H•D2)
4.7.8 Programming notes
4.8 Clock Timer
4.8.1 Configuration of clock timer
4.8.2 Data reading and hold function
4.8.3 Interrupt function
4.8.4 I/O memory of clock timer
4.8.5 Programming notes
4.9 Stopwatch Timer
4.9.1 Configuration of stopwatch timer
4.9.2 Count-uppattern
4.9.3 Interrupt function
4.9.4 I/O memory of stopwatch timer
4.9.5 Programming notes
4.10 Programmable Timer
4.10.1 Configuration of programmable timer
4.10.2 Setting of initial value and counting down
4.10.3 Counter mode
4.10.4 Setting of input clock in timer mode
4.10.5 Interrupt function
4.10.6 Setting of TOUT output
4.10.7 Transfer rate setting for serial interface
4.10.8 I/O memory of programmable timer
CKSEL0: Prescaler 0 source clock selection register (FFC1H•D0)
CKSEL1: Prescaler 1 source clock selection register (FFC1H•D1)
EVCNT: Timer 0 counter mode selection register (FFC0H•D2)
FCSEL: Timer 0 function selection register (FFC0H•D1)
PLPOL: Timer 0 pulse polarity selection register (FFC0H•D0)
RLD00–RLD07:Timer 0 reload data register (FFC4H, FFC5H)
RLD10–RLD17:Timer 1 reload data register (FFC6H, FFC7H)
PTD00–PTD07:Timer 0 counter data (FFC8H, FFC9H)
PTRST0: Timer 0 reset (reload) (FFC2H•D1)
PTRST1: Timer 1 reset (reload) (FFC3H•D1)
PTRUN0: Timer 0 RUN/STOP control register (FFC2H•D0)
PTRUN1: Timer 1 RUN/STOP control register (FFC3H•D0)
CHSEL: TOUT output channel selection register (FFC1H•D3)
EIPT0: Timer 0 interrupt mask register (FFE2H•D0)
EIPT1: Timer 1 interrupt mask register (FFE2H•D1)
IPT0: Timer 0 interrupt factor flag (FFF2H•D0)
IPT1: Timer 1 interrupt factor flag (FFF2H•D1)
4.10.9 Programming notes
4.11 Serial Interface
4.11.1 Configuration of serial interface
4.11.2 Mask option
4.11.3 Transfer modes
Clock synchronous master mode
Clock synchronous slave mode
7-bitasynchronous mode
8-bitasynchronous 8-bitmode
4.11.4 Clock source
4.11.5 Transmit-receivecontrol
4.11.6 Operation of clock synchronous transfer
Data transmit procedure
Data receive procedure
Transmit/receive ready (SRDY) signal
Timing chart
4.11.7 Operation of asynchronous transfer
Page
Page
Receive error
4.11.8 Interrupt function
Transmit completion interrupt
Receive completion interrupt
Error interrupt
4.11.9 I/O memory of serial interface
Table 4.11.9.1(b) Serial interface control bits
Sets P10–P13to the input/output port for the serial interface
When "1" is written: Serial interface
PUL10: Serial interface (1) SIN pull-upcontrol register (FF45H•D0)
PUL12: Serial interface (1) SCLK pull-upcontrol register (FF45H•D2)
PUL30: Serial interface (2) SIN pull-upcontrol register (FF4DH•D0)
PUL32: Serial interface (2) SCLK pull-upcontrol register (FF4DH•D2)
SMD0, SMD1: Serial interface (1) mode selection register (FF70H•D1, D2)
EPR: Serial interface (1) parity enable register (FF71H•D3)
EPRS: Serial interface (2) parity enable register (FF59H•D3)
PMD: Serial interface (1) parity mode selection register (FF71H•D2)
PMDS: Serial interface (2) parity mode selection register (FF59H•D2)
TXEN: Serial interface (1) transmit enable register (FF72H•D0)
RXEN: Serial interface (1) receive enable register (FF72H•D2)
RXENS: Serial interface (2) receive enable register (FF5AH•D2)
RXTRG: Serial interface (1) receive trigger/status (FF72H•D3)
RXTRGS: Serial interface (2) receive trigger/status (FF5AH•D3)
TRXD0–TRXD7:Serial interface (1) transmit/receive data (FF74H, FF75H)
During receiving
OER: Serial interface (1) overrun error flag (FF73H•D0)
OERS: Serial interface (2) overrun error flag (FF5BH•D0)
PER: Serial interface (1) parity error flag (FF73H•D1)
PERS: Serial interface (2) parity error flag (FF5BH•D1)
FER: Serial interface (1) framing error flag (FF73H•D2)
FERS: Serial interface (2) framing error flag (FF5BH•D2)
4.11.10 Programming notes
4.12 Sound Generator
4.12.1 Configuration of sound generator
4.12.2 Buzzer output circuit
4.12.3 Control of buzzer output
4.12.4 Setting of buzzer frequency and sound level
4.12.5 Digital envelope
4.12.6 One-shotoutput
4.12.7 I/O memory of sound generator
BZE: BZ output control register (FF6CH•D0)
BZFQ0–BZFQ2:Buzzer frequency selection register (FF6EH•D0–D2)
BDTY0–BDTY2:Duty level selection register (FF6FH•D0–D2)
ENRST: Envelope reset (FF6CH•D2)
ENON: Envelope ON/OFF control register (FF6CH•D1)
ENRTM: Envelope releasing time selection register (FF6CH•D3)
4.12.8 Programming notes
4.13 SVD (Supply Voltage Detection) Circuit
4.13.1 Configuration of SVD circuit
4.13.2 Mask option
4.13.3 SVD operation
4.13.4 I/O memory of SVD circuit
4.13.5 Programming notes
4.14 Telephone Function (Tone/Pulse Dialer)
4.14.1 Configuration of tone/pulse dialer
4.14.2 Mask option
4.14.3 Operation of telephone function
(2)Executing
(3)Interrupt
4.14.4 Tone mode (DTMF)
Page
Page
4.14.5 Pulse mode (DP)
Page
Page
4.14.6 Pause
Page
4.14.7 Flash
4.14.8 Hold-line
4.14.9 Interrupt
4.14.10 I/O memory of telephone function
Page
OSCC: OSC3 oscillation control (FF00H•D2)
TPS: Tone/Pulse mode selection (FF10H•D3)
MB: Make/Break ratio selection (FF10H•D1)
DRS: Dialing pulse rate selection (FF10H•D0)
PTS0–PTS3:Pause time selection (FF11H)
FTS0–FTS3:Flash time selection (FF12H)
HOLD: Hold-linefunction (FF14H•D2)
PAUSE: Pause function (FF14H•D1)
FLASH: Flash function (FF14H•D0)
HF: Handfree (FF14H•D3)
IDP0–IDP3: Inter-digitpause time selection (FF15H)
SINR: DTMF row frequencies output enable (FF16H•D1)
SINC: DTMF column frequencies output enable (FF16H•D0)
TCD0–TCD3:Telephone code for dialing (FF17H)
(1)Pulse mode
(2)Tone mode
CRMUT: Receive mute control (FF18H•D1)
CTMUT: Transmit mute control (FF18H•D0)
HSON: Hook switch ON/OFF (FF18H•D0)
CTO: Continuous output tone selection (FF16H•D3)
EID: Interrupt mask register (FFE9H•D0)
4.14.11 Programming notes
4.15 FSK Demodulator
4.15.1 Configuration of FSK demodulator
Page
4.15.2 Mask option
4.15.3 Ring/carrier detection and interrupt
4.15.4 Inputting FSK data
Page
4.15.5 I/O memory of FSK demodulator
CDET: Carrier detection bit (FF66H•D0)
RDETCP: RDET comparison register (FF67H•D1)
CDETCP: CDET comparison register (FF67H•D0)
EIRDET, EICDET: Interrupt mask registers (FFEAH•D1, D0)
IRDET, ICDET: Interrupt factor flags (FFFAH•D1, D0)
4.15.6 Programming notes
4.16 Interrupt and HALT
Fig. 4.16.1 Configuration of the interrupt circuit
4.16.1 Interrupt factor
4.16.2 Interrupt mask
4.16.3 Interrupt vector
4.16.4 I/O memory of interrupt
Table 4.16.4.1(b) Control bits of interrupt (2)
Refer to Section 4.14, "Telephone Function
RDETCP, CDETCP: RDETP, CDET comparison registers (FF67H•D1, D0)
Refer to Section 4.15, "FSK Demodulator
EIPT1, EIPT0: Interrupt mask registers (FFE2H•D1, D0)
4.16.5 Programming notes
5.1 Notes for Low Current Consumption
5.2 Summary of Notes by Function
Output port
I/O port
LCD driver
Clock timer
Stopwatch timer
Serial interface (1), (2)
Sound generator
SVD circuit
Telephone function
FSK demodulator
5.3 Precautions on Mounting
<Arrangement of Signal Lines
<Precautions for Visible Radiation (when bare chip is mounted)
CHAPTER 6 BASIC EXTERNAL WIRING DIAGRAM
CHAPTER 7 ELECTRICAL CHARACTERISTICS
Absolute Maximum Rating
7.2 Recommended Operating Conditions
7.3 DC Characteristics
7.4 Analog Circuit Characteristics and Power Current Consumption
7.5 Oscillation Characteristics
7.6 Serial Interface (1), (2) AC Characteristics
7.7 FSK Demodulator Characteristics
7.8 Telephone Function Characteristics
7.9 Timing Chart
7.10 Characteristic Curves (reference value)
High level output current (SEGxx)
Low level output current (SEGxx)
CHAPTER 8 PACKAGE
8.1 Plastic Package
8.2 Ceramic Package for Test Samples
CHAPTER 9 PAD LAYOUT
9.1 Diagram of Pad Layout
Pad Coordinates
EPSON ELECTRONICS AMERICA, INC
- HEADQUARTERS
- SALES OFFICES
West
Central
“Saving” Technology
Epson IS energy savings
S1C63558
Technical Manual