Table 5.2 Parallel interface signals (continued)
Connector | Return |
| Signal |
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| |
pin | line pin | Compati mode | Direction | Description | ||
number | number |
| Nibble mode |
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| |
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17 | 35 |
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|
| Input | Reserved (*1) |
Auto Feed XT | ||||||
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|
| Host Busy |
| Reverse data transfer phase: | |
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| This signal is set low when the host can receive data, |
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| and goes high when the host has received data. |
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| Following a reverse data transfer, the interface enters |
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| the reverse idle phase when the Host Busy signal goes |
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| low and the printer has no data. |
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| Reverse idle phase: |
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| This signal goes high when the Printer Clock signal |
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| goes low so that the interface |
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| data transfer phase. If it goes high with the 1284 |
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| Active signal low, the 1284 idle phase is aborted and |
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| the interface returns to the compatibility mode. |
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18 | – |
| – | Input | Host Logic High | |
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19 to 35 | – | Signal Ground (SG) | – | |||
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36 | – |
| – | Output | Peripheral Logic High | |
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*1 Assigned as a signal name, without any function.
Notes:
1.
2.The direction (input and output) refers to the printer.
3.Return line: