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| Contents | |
| 4.6.4 | Digital PLL circuit | |
| 4.7 Servo Control | ||
| 4.7.1 | Servo control circuit | |
| 4.7.2 | ||
| 4.7.3 | Servo frame format | |
| 4.7.4 | Actuator motor control | |
| 4.7.5 | Spindle motor control | |
CHAPTER 5 | Interface | ||
| 5.1 Physical Interface | ||
| 5.1.1 | Interface signals | |
| 5.1.2 | Signal interface regulation | |
| 5.1.2.1 Out of band signaling | ||
| 5.1.2.2 | Primitives descriptions | |
| 5.1.3 | Electrical specifications | |
| 5.1.4 | Connector pinouts | |
| 5.2 Logical Interface | ||
| 5.2.1 | Communication layers | |
| 5.2.2 Outline of the Shadow Block Register | ||
| 5.2.3 Outline of the frame information structure (FIS) | ||
| 5.2.3.1 | FIS types | |
| 5.2.3.2 | Register - Host to Device | |
| 5.2.3.3 | Register - Device to Host | |
| 5.2.3.4 DMA Active - Device to Host | ||
| 5.2.3.5 DMA Setup - Device to Host or Host to Device (Bidirectional) | ||
| 5.2.3.6 | BIST Active - Bidirectional | |
| 5.2.3.7 Data - Host to Device or Device to Host (Bidirectional) | ||
| 5.2.4 | Shadow block registers | |
| 5.3 Host Commands | ||
| 5.3.1 Command code and parameters |
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