Gateway ALR 9200 Field, Options, Description, Advanced Chipset Control Submenu, Table 17: Advanced Chipset Control Submenu

Advanced Chipset Control Submenu

The advanced chipset control submenu provides several fields that allow you to control various advanced features of the chipset. Table 17 lists the fields and the options for each.

Table 17: Advanced Chipset Control Submenu

Field	Options	Description
Address Bit	Disabled	To be enabled, there must be a power of 2 number
Permuting	Enabled	of rows (2, 4, 8, or 16), all rows must be the same
		size, and all populated rows must be adjacent and
		start at row 0. Two-way or four-way permuting is
		set automatically based on memory configuration.
Base RAM Step	1 MB	Tests base memory once per MB, once per KB, or
	1 KB	at every location.
	Every location
Extended RAM	1 MB	Tests extended memory once per MB, once per
Step	1 KB	KB, or at every location.
	Every location
L2 Cache	Enabled	When enabled, the secondary cache is sized and
	Disabled	enabled. For Core Clock Frequency-to-System
		Bus ratios equal to two, BIOS automatically
		disables the L2 cache.
ISA Expansion	Enabled	When enabled, every I/O access with an address in
Aliasing	Disabled	the range x100-x3FFh, x500-x7FFh, x900-xBFF,
		and xD00-xFFFh is internally aliased to the range
		0100-03FFh before any other address range
		checking is performed.
Memory Scrubbing	Disabled	When enabled, BIOS automatically detects and
	Enabled	corrects single bit errors (SBEs).
Restreaming Buffer	Enabled	When enabled, the data returned and buffered for
	Disabled	a Delayed Inbound Read can be reaccessed
		following a disconnect.
Read Prefetch for	N/A	Informational field only. Configures the number of
PXB0A		Dwords that are prefetched on Memory Read
		Multiple commands.
Read Prefetch for	N/A	Informational field only. Configures the number of
PXB0B		Dwords that are prefetched on Memory Read
		Multiple commands.

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