HP VXI E1432A 176

HP E1432A User's Guide

Register Definitions

Data Ready: A one (1) indicates that there is at least one word (32 bits) of data available in the Send Data register. A zero (0) indicates that there is not valid data in the Send Data register.

ST Done: A one (1) indicates that the internal DSP has competed and passed its self test.

Loaded: A one (1) indicates that the internal DSP has successfully booted and has loaded a valid model code.

Done: A zero (0) indicates that the on-card microprocessor has not finished processing the last command and the Err* bit is not valid. This bit is set and cleared by the DSP.

Err*: A zero (0) indicates that an error has occurred in communicating

with the DSP (for example: invalid parameters). This bit is set and cleared by the DSP.

Ready: The meaning of this depends on the state of the Passed bit. While Passed is false, a one(1) indicates that the device is in the Config Reg Init state and the Model Code bits of the Device Type register are not valid, while a zero (0) indicates that the device is in either the self test or failed state. When Passed is true, a one (1) indicates that the DSP has finished its initialization and is ready for normal operation, while a zero (0) indicates that the device is in the passed state.

Passed: A zero (0) indicates that the device is in either the Hard Reset, Soft Reset, Config Reg Init, Failed, or Init Failed state. A one (1) indicates that the device is in the passed state.

HW OK: A one (1) indicates that all the on-card FPGAs have successfully be initialized.

Q Resp Ready (Query Response Ready): A one (1) indicates that the Query Response Register is loaded and ready to be read. It is set by the DSP and cleared in hardware by a write to the Command Register.

Cmd Ready: A one (1) indicates that the command register and parameter register are available for writing. It is set by the DSP microprocessor and cleared in hardware by a write to the Command Register. This bit, when zero (0) additionally indicates that the Done bit is not valid.

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Contents

Page Page Page Page In This Book 1 Installing the HP E1432A Installing the HP E1432A To inspect the HP E1432A To install the HP E1432A Install the host interface libraries 3 Using the HP E1432A What is VXIplug&play Header and Library Files Channels and groups Multiple-module/mainframeMeasurements 4 The C-LanguageHost Interface Library Parameter Information Multiple-module/MainframeMeasurements 5 Module Description HP E1432A Front Panel Description 6 The Arbitrary Source Option (1D4) Arbitrary Source Description The Arbitrary Source Option Front Panel 7The Tachometer Option (AYF) Tachometer Description 9 Troubleshooting the HP E1432A Diagnostics 10 Replacing Assemblies Replaceable Parts To remove the top cover Page Page Page Caution Page Page Page Page Page Page Page System Requirements (Microsoft Windows95 and NT) •Software is supplied on CD-ROM System Requirements (HP-UX10.20) •One of the following workstations: •Software is supplied on CD-ROM,so a CD-ROMdrive is needed Getting Updates Via FTP (HP-UX) Getting Updates Via FTP (Windows) Page To install the HP-UXVXIplug&play drivers for the HP E1432A (for HP-UXsystems): The Resource Manager Using the soft front panel The buttons on the right side of the SFP display are defined as follows: This button opens the Measurement Control dialog box. You can set: There is a checkbox to make all channels identical Page scope.vee Page Page Page minimum.vee Page Other HP VEE example programs The files in the examples directory are: Makefile directory README A file containing the information given here Running a demo program: semascope.c Page Page Page Page Overview VXIplug&play drivers The HP E1432A VXIplug&play driver is based on the following architecture: Figure 3-7:VXI Plug&Play driver architecture It is most useful to discuss this architecture from the bottom up Manufacturer and model codes The following are the Hewlett-PackardVXI models in this file: Model Name The Soft Front Panel (SFP) Page Channel Groups Initialization Creating a Channel Group Input, Source, and Tach Channels Page Page Page The cable adds approximately 6 ns per meter of cable MXI Bus Cable Figure 10: Multiple mainframes - three mainframes Page Data Flow Diagram and FIFO Architecture trigger host Static port RAM trigger Figure 3-11:Data flow and FIFO architecture VME Bus Local Bus Base Sample Rates z e ro to Page Page Sync/Trigger line Idle Trigger Arm Meas Idle Page Page Page trigger type Page Page Page Interrupt Setup Interrupt Mask Bit Definitions Define (in e1432.h) HPE1432_IRQ_TRIGGER HP E1432A Interrupt Handling This is a summary of how to set up an HP E1432A interrupt: HP E1432A interrupts with hpe1432_reenableInterrupt. The call to Page Page Auto range Averaging Continuous re-sampleddata Fast span or range change Time arming Zoom (HP E1432A only) Zoom (for the Arbitrary Source, option 1D4) The Function Reference for VXIplug&play The Function Reference for the Host Interface Library (C-languageversion) Page Page Page Header and Library Files lib1432.a E1432A hardware lib1432.sl program smaller Description of HP E1432A Parameters Global Parameters Page 51.2 kHz 4-channelInput Parameters Option 1D4 Single-channelSource Parameters Option AYF Tachometer Parameters Channel and Group IDs Page Page Page Page Page INTX Figure 4-2:Multiple mainframes - three mainframes Page Sync/Trigger line Idle Trigger Arm Meas Page Page Page Page enabling function Page Page Page This is a summary of how to set up SICL to receive an HP E1432A interrupt: Page For More Information Page Page Module Description General Features Arbitrary Source Features (option 1D4) Tachometer Features (option AYF) Other Options LBUS/FIFO Bus connector micro Abus Bbus Page Front Panels for 4, 8, and 16 Channels Standard Front Panel Page Power Supplies and Ground Data Transfer Bus DTB Arbitration Bus Priority Interrupt Bus Utility Bus The Local Bus (Option UGV) Address Space Shared Memory Memory Map Page List of A16 Registers Read Write 3E16 3C16 Trigger Lines (TTLTRG) Sync/Trigger line Free-runningclock line VXI bus External Sample Providing an External Clock HP E1432A Substrate Input circuitry DC Voltage Reference from Page Page Trigger Arbitrary Output Source Output Modes COLA (and Summer) External Shutdown DAC circuitry Digital input filter Page LED’s and Connectors for the Arbitrary Source Option Updating the arbitrary source firmware Page Page Tachometer Inputs External Trigger Input Tachometer Monitoring Exact RPM Triggering Input Count Division Holdoff Time Analog 32-bit Latch Page LED’s and Connectors for the Tachometer Option Page Page Service Page HP E1432-61602 Voltage-typeBreak Out Box HP E1432-61600 ICP-typeBreak Out Box Break Out Box Grounding Making a Custom Break Out Box Cable Backshell kit, plug Cable Connector, plug Shielded cable part number AMP pin pin # +Diff + Diff Recommendations on wiring for the E1432/3A 4 Channel Input Connector Page I2C_EN I2C_SDA I2C_SCL BOB_EN CAL_LOW Page Page Display usage message Print version info Hostdiag returns 0 upon success, or returns non-zeroif an error is detected Coverage: Notes: Page Page Replacement parts are listed in the following tables: Ordering Information Direct Mail Order System Code Numbers Assemblies: without option AYF or 1D4 Ref HP Part Mfr Des Assemblies: with option AYF Page Assemblies: with option 1D4 Page Cables: without option AYF or 1D4 Cables: with option AYF Cables: with option 1D4 Front Panel Page Page Page Page Page Page Page Page Page Page Page Page Main PC assembly change Page The A16 Registers A-3 The A24 Registers 7FFFF16 2FFFF16 1FFFF16 0003 F16 The VXI Bus Registers are defined as follows: (HP’s ID) (1MB of A24) Active Err Page Enable Sysfail Inhibit: A one (1) disables the device from driving the SYSFAIL* line Reset: A one (1) forces the device into a reset state LBus Enable: Writing a one (1) enables the Local Bus interface. Writing a zero (0) disables the local bus interface. RESET VALUE: Bit 0: DSP A(17) Bit 1: DSP A(18) Bit 2: Logical Address: This is the device’s current logical address 32-bitRegisters 1Always read all 32 bits of a 32-bitregister 2Always read the most significant part first Page Command/Response Protocol The Command/Response protocol uses the following resources: Page DSP Protocol DSP Bus Registers 200A Spare ST Done Loaded The DSP Command register has the following format: Rev. April Specifications 2 of 3 of 4 of Option 1D4 Arbitrary Source 5 of 6 of 7 of Option AYF Tachometer Input 8 of VXI System Level Specifications 9 of 10 of 11 of Specification Note Warranty Information Abbreviations Fs = sample rate of ADC Fc = cut off frequency of high pass or low pass filters Page Page Page Page Page Page Page Page Page Index Page Page Page Page Page Page Page Page declares, that the product conforms to the following specifications: EMC: Supplementary Information: