HP E1432A User's Guide
Register Definitions
Parameter 1-7 Registers: These are 32-bit RAM locations used to pass parameters along with commands to the device or query responses from the device. See the following section regarding D16/D08 access of 32-bit registers and the communication protocol.
32-bit Registers
Several of the A16 registers (and all other 24-bit registers) are implemented as 32-bit-only resources. These are accessible using VME Bus D16 and D08(EO) accesses. However certain restrictions apply. The affected A16 registers are:
RAM 0-1
Send Data
Receive Data
Query Response Command
Parameter 1-7
Reading 32-bit Registers
When reading a 32-bit register using 8- or 16-bit modes, a simple caching mechanism is used. On any read including the most significant byte (lowest address), the 32-bit register is read and all 32-bits are latched into the read cache. A read not including the most significant byte fetches data from the read cache, without re-reading the register. This insures that the data will be unchanged by any intervening write by the DSP (which would result in garbled data).
This mechanism also introduces a hazard. Reads of less significant bytes get data from the 32-bit register last read by a most-significant-byte read. In other words, you can’t read the least significant byte first, or by itself. Thus there are two important rules:
1Always read all 32 bits of a 32-bit register.
2Always read the most significant part first.
