
Specifications
Figure | to Figure |
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Performance | Specifications |
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| Cycle |
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Device |
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| Time | (ns) |
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Microprocessor | (66 | ns | clock) |
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Access | to | RAM: | ñ |
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| Memory | read | Page |
| hit, |
| burst | 240 | ns |
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| Page | miss, | burst |
| 360 | ns |
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| Memory | write | Page | miss, | burst | 45 |
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Access | to | ROM | : |
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| 1000 |
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Refresh | rate | (typically | performed | µeverys) | 15.6 750 |
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DMA | controller | (4 | µs | clock) | : |
| 1250 |
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Bus | cycles | (AT) : |
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| 8 bit |
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| 1000 |
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| 16 bit |
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| 625 |
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ñ | The | cycle | times | shown | for | access to | are | based on 70 | ns | |||||||
| EDO | memory. |
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| Cycle |
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Device |
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| Time | (ns) |
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Microprocessor (60 |
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| Memory | read | Page |
| hit, |
| burst | 216 | ns |
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| Page | miss, | burst |
| 350 | ns |
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| Memory | write | Page | miss, | burst | 50 | ns |
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