IBM 560E manual Microprocessor, Cache Memory Operation, Description, main

Models: 560 560E

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Microprocessor

Description

This section describes the microprocessor, connectors, memory subsystems, and miscellaneous system functions and ports for the ThinkPad computers. You can find additional information about these topicsIBM inPersonal System/2 Hardware Interface Technical Reference–AT-Bus Subsystems.

Microprocessor

The ThinkPad 560 uses the Intel Pentium 100/120/133MHz microprocessor. This microprocessor contains a full 32-bit RISC integer core, a built-in math coprocessor, and a 16KB internal cache memory.

The

ThinkPad 560E uses the Intel Pentium 150/166MHz

microprocessor with the MMX technology. This microprocessor

contains

a

full 32-bit RISC

integer core, a built-in math coprocessor,

and

a

32KB

on-chip cache

memory.

Cache Memory Operation

The cache memory in the Intel Pentium microprocessor enables the microprocessor to read instructions and data much faster than if the

microprocessor

had

to

access

system

memory. When

an

instruction

 

 

is

first used

or data is first read or written,

it is transferred to the

cache

memory

from

main

memory. This

enables

future

accesses

to

 

 

the

instructions or data to occur much faster.

 

 

 

 

 

 

 

 

The

cache

is

 

disabled

and

empty

when

the

microprocessor

comes

 

 

out

of the reset state. The cache is tested

and

enabled

during

the

power-on self-test (POST).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The

cache

memory in the Intel Pentium microprocessor

is

 

loaded

 

 

from

system memory in 32-byte increments, each referred

to

as

a

 

cache line. A cache line is aligned on a paragraph boundary. A

 

 

 

reference

to

 

any

byte

contained

in

a

cache line

results

in the

entire

line

being

read into the cache memory (if the data

was

not

already in

the

cache). When the microprocessor

gives

up

control

of

 

the

system

 

bus,

the

cache memory enters “snoop” mode and monitors all write

 

and

read

operations. If

memory data

is

 

written

to

a

location

in the

cache

and

the

cache line is in the “modified”

state,

the

corresponding

cache

line

is

 

written back to system memory and

is

invalidated.

 

2-2

ThinkPad

560/560E

System

Board

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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IBM 560E manual Microprocessor, Cache Memory Operation, Description, main