Status Register | B (Hex | 00B) |
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Bit | Function |
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7 | Set |
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6 | Enable | periodic interrupt |
5 | Enable | alarm interrupt |
4 | Enable | |
3 | Enable | square wave |
2 | Date | mode |
1 | ||
0 | Enable | |
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Figure | Register | B | (Hex 00B) |
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Bit | 7 | When | set | to | 0, | this | bit | updates | the | cycle, | normally | by | ||||||||||||||
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| advancing | the count at a rate |
| of | one | cycle | per |
| second. | ||||||||||||||||
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| When set to 1, it immediately ends any update cycle in | ||||||||||||||||||||||||
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| progress, | and the program can initialize the 14 |
| time | bytes | ||||||||||||||||||||
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| without | any | further | updates | occurring | until | this | bit | is set | ||||||||||||||||
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| to | 0. |
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Bit | 6 | This | is |
| a | read/write | bit | that | allows | an | interrupt |
| to | occur at | ||||||||||||
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| a rate specified by the rate and divider bits in status | ||||||||||||||||||||||||
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| register | A. When set to 1, | this bit | enables the | interrupt. | ||||||||||||||||||||
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| The | system | initializes | this | bit | to | 0. |
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Bit | 5 | When | set | to 1, this bit enables the | alarm |
| interrupt. The | |||||||||||||||||||
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| system | initializes | this | bit | to |
| 0. |
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Bit | 4 | When set to 1, this bit enables the |
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| interrupt. The | system | initializes | this | bit | to | 0. |
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Bit | 3 | When set to 1, this bit enables the |
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| frequency as set by the | ||||||||||||||||||||||||
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| register | A. The system initializes this bit to 0. |
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Bit | 2 | This | bit | indicates |
| whether | the |
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| or binary format is used for |
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| updates. When set to 1, this bit indicates the binary | ||||||||||||||||||||||||
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| format. The | system | initializes | this | bit | to 0. |
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Bit | 1 | This | bit | indicates |
| whether | the | hours | byte | is | in |
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| mode. When |
| set | to | 1, | this | bit indicates | the | |||||||||||||||||
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| mode. The | system | initializes | this | bit | to |
| 1. |
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