System | Control Port | B | (Hex | 0061) |
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Bit | definitions |
| for | the write | and | read functions of this port are shown | |||||
in | the | following | figures: |
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| Reserved |
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| 3 | Reserved | (should | be | 0) |
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| 2 | Enable | parity | check |
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| 1 | Enable | speaker | data |
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| 0 |
| Timer 2 gate to speaker |
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Figure |
| Control | Port | B | (Hex | 0061, Write) | |||||
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| Bit | Function |
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| 7 |
| Parity | check |
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| 6 |
| Channel | check |
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| 5 |
| Timer | 2 | output |
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| 4 | Toggles with each refresh request |
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| 3 | Reserved |
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| 2 | Enable | parity | check |
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| 1 | Enable | speaker | data |
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| 0 |
| Timer | 2 | gate | to | speaker |
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Figure 2-31. System Control Port B (Hex 0061, Read)
Bit 7 When set to 1, this bit indicates that the PCI System Error (SERR#) was pulsed active.
Bit 6 When set to 1, this bit indicates a channel check has occurred.
Bit 5 When read, this bit indicates the condition of the timer/counter 2 ‘output’ signal.
Bit | 4 | When read, this bit toggles for each refresh request. | |||||||||
Bit | 3 | Reserved. |
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Bit | 2 | When | set | to | 0, | this | bit | enables | the | PCI System Error | |
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| (SERR#). This | bit | is set to 1 during | a | ||||||
Bit | 1 | When | set | to | 1, | this | bit | enables | the | speaker | data. |
Bit | 0 | When | set | to | 1, | this | bit | enables | the | timer 2 | gate. |
ThinkPad 560/560E System Board