Cont | IBM EM78P259N/260N specs

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.1.3.1Data Memory Configuration

	Address		R PAGE registers		IOCX0 PAGE registers		IOCX1 PAGE registers
	00	R0	(Indirect Addressing Register)			Reserve		Reserve
	01	R1	(Time Clock Counter)		CONT	(Control Register)		Reserve
	02	R2	(Program Counter)			Reserve		Reserve
	03	R3	(Status Register)			Reserve		Reserve
	04	R4	(RAM Select Register)			Reserve		Reserve
	05	R5	(Port 5)		IOC50 (I/O Port Control Register)		IOC51	(TCCA Counter)
	06	R6	(Port 6)		IOC60 (I/O Port Control Register)		IOC61	(TCCB LSB Counter)
	07	R7	(Port 7)		IOC70 (I/O Port Control Register)		IOC71	(TCCB HSB Counter)
	08	R8	(ADC Input Select Register		IOC80	(Comparator and TCCA	IOC81	(TCCC Counter)
						Control Register)
	09	R9	(ADC Control Register)		IOC90	(TCCB and TCCC	IOC91	(Low Time Register)
						Control Register)
	0A	RA	(ADC Offset Calibration		IOCA0	(IR and TCCC Scale	IOCA1	(High Time Register)
	0A	RA	Register)		IOCA0	Control Register)	IOCA1	(High Time Register)
	0B	RB	(The converted value		IOCB0	(Pull-down Control	IOCB1	(High Time and Low Time
			AD11~AD4 of ADC)			Register)		Scale control Register)
	0C	RC	(The converted value		IOCC0	(Open-drain Control	IOCC1	(TCC Prescaler Control)
		RC	AD11~AD8 of ADC)			Register)
			AD11~AD8 of ADC)			Register)
	0D	RD	(The converted value		IOCD0 (Pull-high Control Register)			Reserve
	0D	RD	AD7~AD0 of ADC)		IOCD0 (Pull-high Control Register)			Reserve
			AD7~AD0 of ADC)			(WDT Control Register and
	0E	RE	(Interrupt Status 2 and		IOCE0	(WDT Control Register and		Reserve
			Wake-up Control Register			Interrupt Mask Register 2)
	0F	RF (Interrupt Status Register 1)			IOCF0 (Interrupt Mask Register 1)			Reserve
	10
	︰		General	Registers
	1F
	20		Bank 0	Bank 1
	：		Bank 0	Bank 1
	3F

Product Specification (V1.2) 05.18.2007

• 7

(This specification is subject to change without further notice)

Image 13

IBM EM78P259N/260N manual Bit Microprocessor with OTP ROM Data Memory Configuration, Cont

Contents

EM78P259N/260N Elan Microelectronics Corporation Contents TCC/WDT and Prescaler Reset and Wake-upAnalog-To-Digital Converter ADC 6.1 11.2 11.111.3 11.4 Date Doc. Version Revision Description General Description FeaturesBit Microprocessor with OTP ROM Pin Assignment Block DiagramPin DIP/SOP Pin DIP/SOP/SSOP Pin Description Symbol Pin No Type FunctionEM78P259NP/M EM78P260NP/M/KM Operational Registers Function Description1 R0 Indirect Address Register 2 R1 Time Clock /Counter EM78P259N/260N Cont Bit Microprocessor with OTP ROM Data Memory Configuration Bit 4 T 5 R4 RAM Select RegisterBit Bits 5~0 6 R5 ~ R6 Port 5 ~ Port Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode7 R7 Port Bit 7 ~ Bit 8 R8 Aisr ADC Input Select Register Bit 3 Adpd 9 R9 Adcon ADC Control Register RB Addata Converted Value of ADC RA Adoc ADC Offset Calibration RegisterBit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits Bit 2 ~ Bit 0 Unimplemented, read as ‘0’ RD ADDATA1L Converted Value of ADC RC ADDATA1H Converted Value of ADCRE Interrupt Status 2 & Wake-up Control Register 16 R10 ~ R3F RF Interrupt Status 2 RegisterAll of these are 8-bit general-purpose registers Accumulator Special Purpose RegistersControl Register 4 IOC80 Comparator and Tcca Control Register 3 IOC50 ~ IOC70 I/O Port Control RegisterBit 7 & Bit 6 Not used Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bits Bit 4 Tccbte Tccb signal edge Bit 6 Tccben Tccb enable bit 0 = disable TccbTccc signal source Bit 0 Tcccte Tccc signal edge IOCA0 IR and Tccc Scale Control Register Bit 2 HF Bit 3 IREBit 1 LGP Bit 0 Iroute IOCC0 Open-Drain Control Register IOCB0 Pull-down Control RegisterBit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60 IOCE0 WDT Control & Interrupt Mask Registers IOCD0 Pull-high Control RegisterBit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 = Disable Lpwtif interrupt Lpwtif interrupt enable bit= Enable Lpwtif interrupt IOCF0 Interrupt Mask Register 13 IOC61 Tccb Counter 12 IOC51 Tcca Counter 15 IOC81 Tccc Counter 14 IOC71 TCCBH/MSB Counter IOCA1 High Time Register 16 IOC91 Low Time RegisterIOCB1 High/Low Time Scale Control Register Bit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bits IOCC1 TCC Prescaler CounterTCC prescaler counter can be read and written to TCC/WDT and Prescaler MUX I/O Ports I/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Reset and Wake-up Operation Reset and Wake-upUsage of Port 5 Input Change Wake-up/Interrupt Function Wake-up Wake-up and Interrupt EM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Following summarizes the initialized values for registers Address Name Reset Type Bit Name Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Tcif Controller Reset Block Diagram T and P Status under Status R3 Register InterruptEvent EM78P259N/260N Interrupt Vector Interrupt Status Priority Reti ADC Control Register AISR/R8, ADCON/R9, ADOC/RA Analog-to-Digital Converter ADC1.1 R8 Aisr ADC Input Select Register Bit 7 ~ Bit 3 ADE3 Bit 2 ADE2 P54/TCC/VREF Pin Priority High Medium Low 1.2 R9 Adcon AD Control RegisterP54 = ADC is operating While the CPU is operatingRA Adoc AD Offset Calibration Register ADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD ADC Operation during Sleep ModeADC Sampling Time AD Conversion Time Programming Process Programming Process/ConsiderationsFollow these steps to obtain data from the ADC Define a Control Register Sample Demo Programs Define a General RegisterADC Control Register Define Bits in Adcon AD power on Overview Infrared Remote Control Application/PWM Waveform Generation Fcarrier Function Description IRE Irout IR/PWM Related Status/Data Registers Programming the Related RegistersAddress Name Bit EM78P259N/260N Under Tcca Counter IOC51 Timer/CounterUnder Tccb Counter IOC61 Under Tccc Counter IOC81 Related Tccx Status/Data Registers Comparator Comparator Output External Reference Signal Wake-up from Sleep Mode Using a Comparator as an Operation AmplifierComparator Interrupt Oscillator Modes OscillatorOscillator Modes Conditions Oscillator Type Crystal Oscillator/Ceramic Resonators CrystalFrequency C1pF C2pF 18 Serial Mode Crystal/Resonator Circuit Diagram External RC Oscillator Mode Internal Drift Rate RC Frequency Temperature Internal RC Oscillator ModeCext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C 40C ~ +85C 3V~5.5V Total External Power-on Reset Circuit Power-on ConsiderationsProgrammable WDT Time-out Period Vdd Residual Voltage ProtectionEM78P259N EM78P260N Code Option Register Word Code OptionWord Word1 Bit12 ~ Bit0 Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit = Pulses equal to 32/fc s is regarded as signal default = Pulses equal to 8/fc s is regarded as signalBit Microprocessor with OTP ROM Bit 3 HLP Bit 2 ~ 0 PR2 ~ PR0 Protect Bits Instruction Set Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bitsCustomer ID Register Word Instruction Binary Following are the EM78P259N/260N instruction setMnemonic Operation Status Affected Items Rating Absolute Maximum Ratings Symbol Parameter Condition Min Typ Max Unit DC Electrical CharacteristicsTa=25 C, VDD=5.0V±5%, VSS=0V Voltage Min Typ Max Internal RC Drift Rate Vdd=2.5V to 5.5V, Vss=0V, Ta=25C AD Converter Characteristics Device Characteristics Comparator OP CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C Symbol Parameter Conditions Min Typ Max Unit AC Electrical CharacteristicTa=25C, VDD=5V±5%, VSS=0V Reset Timing CLK=0 Timing DiagramsAC Test Input/Output Waveform TCC Input Timing CLKS=0 Package Information Package Type18-Lead Plastic Dual in line Pdip 300 mil Package Type Pin Count Package Size 838 18-Lead Plastic Small Outline SOP 300 mil 650 Lead Plastic Shrink Small Outline Ssop 209 mil Lead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Address Trap Detect Quality Assurance and ReliabilityTest Category Test Conditions Remarks