IOCD0 Pull-high Control Register | IBM EM78P259N/260N specification

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.2.9 IOCD0 (Pull-high Control Register)

	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	/PH57	/PH56	/PH55	/PH54	/PH53	/PH52	/PH51	/PH50

Note: The IOCD0 register is both readable and writable

Bit 7 (/PH57): Control bit is used to enable the pull-high of the P57 pin (applicable to EM78P260N only).

0= Enable internal pull-high;

1= Disable internal pull-high.

Bit 6 (/PH56): Control bit used to enable the pull-high function of the P56 pin (applicable to EM78P260N only).

Bit 5 (/PH55): Control bit used to enable the pull-high function of the P55 pin.

Bit 4 (/PH54): Control bit used to enable the pull-high function of the P54 pin.

Bit 3 (/PH53): Control bit used to enable the pull-high function of the P53 pin.

Bit 2 (/PH52): Control bit used to enable the pull-high function of the P52 pin.

Bit 1 (/PH51): Control bit used to enable the pull-high function of the P51 pin.

Bit 0 (/PH50): Control bit used to enable the pull-high function of the P50 pin.

6.2.10 IOCE0 (WDT Control & Interrupt Mask Registers 2)

	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	WDTE	EIS	ADIE	CMPIE	PSWE	PSW2	PSW1	PSW0

Bit 7 (WDTE): Control bit used to enable Watchdog Timer 0 = Disable WDT

1 = Enable WDT

WDTE is both readable and writable

Bit 6 (EIS): Control bit used to define the function of the P60 (/INT) pin 0 = P60, bi-directional I/O pin

1 = /INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit 0 of IOC60) must be set to "1"

NOTE

■When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig. 6-4 (I/O Port and I/O Control Register Circuit for P60 (/INT)) under Section 6.4 (I/O Ports).

■EIS is both readable and writable.

Product Specification (V1.2) 05.18.2007

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(This specification is subject to change without further notice)

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IBM EM78P259N/260N manual IOCD0 Pull-high Control Register, IOCE0 WDT Control & Interrupt Mask Registers

Contents

EM78P259N/260N Elan Microelectronics Corporation Contents 6.1 Reset and Wake-upTCC/WDT and Prescaler Analog-To-Digital Converter ADC 11.4 11.111.2 11.3 Date Doc. Version Revision Description Features General DescriptionBit Microprocessor with OTP ROM Pin DIP/SOP/SSOP Block DiagramPin Assignment Pin DIP/SOP Symbol Pin No Type Function Pin DescriptionEM78P259NP/M EM78P260NP/M/KM 2 R1 Time Clock /Counter Function DescriptionOperational Registers 1 R0 Indirect Address Register EM78P259N/260N Cont Bit Microprocessor with OTP ROM Data Memory Configuration Bits 5~0 5 R4 RAM Select RegisterBit 4 T Bit Bit 7 ~ Bit Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode6 R5 ~ R6 Port 5 ~ Port 7 R7 Port 8 R8 Aisr ADC Input Select Register Bit 3 Adpd 9 R9 Adcon ADC Control Register Bit 2 ~ Bit 0 Unimplemented, read as ‘0’ RA Adoc ADC Offset Calibration RegisterRB Addata Converted Value of ADC Bit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits RC ADDATA1H Converted Value of ADC RD ADDATA1L Converted Value of ADCRE Interrupt Status 2 & Wake-up Control Register RF Interrupt Status 2 Register 16 R10 ~ R3FAll of these are 8-bit general-purpose registers Special Purpose Registers AccumulatorControl Register Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bits 3 IOC50 ~ IOC70 I/O Port Control Register4 IOC80 Comparator and Tcca Control Register Bit 7 & Bit 6 Not used Bit 0 Tcccte Tccc signal edge Bit 6 Tccben Tccb enable bit 0 = disable TccbBit 4 Tccbte Tccb signal edge Tccc signal source IOCA0 IR and Tccc Scale Control Register Bit 0 Iroute Bit 3 IREBit 2 HF Bit 1 LGP Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60 IOCB0 Pull-down Control RegisterIOCC0 Open-Drain Control Register Bit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 IOCD0 Pull-high Control Register IOCE0 WDT Control & Interrupt Mask RegistersBit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 IOCF0 Interrupt Mask Register Lpwtif interrupt enable bit= Disable Lpwtif interrupt = Enable Lpwtif interrupt 13 IOC61 Tccb Counter 12 IOC51 Tcca Counter 15 IOC81 Tccc Counter 14 IOC71 TCCBH/MSB Counter 16 IOC91 Low Time Register IOCA1 High Time RegisterIOCB1 High/Low Time Scale Control Register IOCC1 TCC Prescaler Counter Bit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bitsTCC prescaler counter can be read and written to TCC/WDT and Prescaler MUX I/O Ports I/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Wake-up Wake-up and Interrupt Reset and Wake-upReset and Wake-up Operation Usage of Port 5 Input Change Wake-up/Interrupt Function EM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Following summarizes the initialized values for registers Address Name Reset Type Bit Name Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Tcif Controller Reset Block Diagram Interrupt T and P Status under Status R3 RegisterEvent EM78P259N/260N Interrupt Vector Interrupt Status Priority Reti Bit 7 ~ Bit 3 ADE3 Bit 2 ADE2 Analog-to-Digital Converter ADCADC Control Register AISR/R8, ADCON/R9, ADOC/RA 1.1 R8 Aisr ADC Input Select Register 1.2 R9 Adcon AD Control Register P54/TCC/VREF Pin Priority High Medium LowP54 While the CPU is operating = ADC is operatingRA Adoc AD Offset Calibration Register AD Conversion Time ADC Operation during Sleep ModeADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD ADC Sampling Time Programming Process/Considerations Programming ProcessFollow these steps to obtain data from the ADC Define Bits in Adcon Sample Demo Programs Define a General RegisterDefine a Control Register ADC Control Register AD power on Overview Infrared Remote Control Application/PWM Waveform Generation Fcarrier Function Description IRE Irout Programming the Related Registers IR/PWM Related Status/Data RegistersAddress Name Bit EM78P259N/260N Timer/Counter Under Tcca Counter IOC51Under Tccb Counter IOC61 Under Tccc Counter IOC81 Related Tccx Status/Data Registers Comparator Comparator Output External Reference Signal Using a Comparator as an Operation Amplifier Wake-up from Sleep ModeComparator Interrupt Conditions OscillatorOscillator Modes Oscillator Modes Crystal Oscillator/Ceramic Resonators Crystal Oscillator TypeFrequency C1pF C2pF 18 Serial Mode Crystal/Resonator Circuit Diagram External RC Oscillator Mode 40C ~ +85C 3V~5.5V Total Internal RC Oscillator ModeInternal Drift Rate RC Frequency Temperature Cext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C Power-on Considerations External Power-on Reset CircuitProgrammable WDT Time-out Period EM78P260N Residual Voltage ProtectionVdd EM78P259N Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit Code OptionCode Option Register Word Word Word1 Bit12 ~ Bit0 Bit 2 ~ 0 PR2 ~ PR0 Protect Bits = Pulses equal to 8/fc s is regarded as signal= Pulses equal to 32/fc s is regarded as signal default Bit Microprocessor with OTP ROM Bit 3 HLP Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bits Instruction SetCustomer ID Register Word Following are the EM78P259N/260N instruction set Instruction BinaryMnemonic Operation Status Affected Items Rating Absolute Maximum Ratings DC Electrical Characteristics Symbol Parameter Condition Min Typ Max UnitTa=25 C, VDD=5.0V±5%, VSS=0V Voltage Min Typ Max Internal RC Drift Rate Vdd=2.5V to 5.5V, Vss=0V, Ta=25C AD Converter Characteristics Comparator OP Characteristics Device CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C AC Electrical Characteristic Symbol Parameter Conditions Min Typ Max UnitTa=25C, VDD=5V±5%, VSS=0V TCC Input Timing CLKS=0 Timing DiagramsReset Timing CLK=0 AC Test Input/Output Waveform Package Type Pin Count Package Size Package TypePackage Information 18-Lead Plastic Dual in line Pdip 300 mil 838 18-Lead Plastic Small Outline SOP 300 mil 650 Lead Plastic Shrink Small Outline Ssop 209 mil Lead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Quality Assurance and Reliability Address Trap DetectTest Category Test Conditions Remarks