Special Purpose Registers, Accumulator | IBM EM78P259N/260N instruction

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.2 Special Purpose Registers

6.2.1 A (Accumulator)

Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register.

6.2.2 CONT (Control Register)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTE

INT

TS

TE

PSTE

PST2

PST1

PST0

Note: The CONT register is both readable and writable

Bit 6 is read only.

Bit 7 (INTE): INT signal edge

0

= interrupt occurs at the rising edge on the INT pin

1

= interrupt occurs at the falling edge on the INT pin

Bit 6 (INT):

Interrupt enable flag

0

= masked by DISI or hardware interrupt

1

= enabled by the ENI/RETI instructions

This bit is readable only.

Bit 5 (TS):

TCC signal source

0

= internal instruction cycle clock. P54 is bi-directional I/O pin.

1

= transition on the TCC pin

Bit 4 (TE):

TCC signal edge

0

= increment if the transition from low to high takes place on the TCC

pin

1

= increment if the transition from high to low takes place on the TCC

pin.

Bit 3 (PSTE): Prescaler enable bit for TCC

0

= prescaler disable bit. TCC rate is 1:1.

1

= prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.

Product Specification (V1.2) 05.18.2007

• 15

(This specification is subject to change without further notice)

Image 21

IBM EM78P259N/260N manual Special Purpose Registers, Accumulator, Control Register

Contents

EM78P259N/260N Elan Microelectronics Corporation Contents TCC/WDT and Prescaler Reset and Wake-upAnalog-To-Digital Converter ADC 6.1 11.2 11.111.3 11.4 Date Doc. Version Revision Description Features General DescriptionBit Microprocessor with OTP ROM Pin Assignment Block DiagramPin DIP/SOP Pin DIP/SOP/SSOP Symbol Pin No Type Function Pin DescriptionEM78P259NP/M EM78P260NP/M/KM Operational Registers Function Description1 R0 Indirect Address Register 2 R1 Time Clock /Counter EM78P259N/260N Cont Bit Microprocessor with OTP ROM Data Memory Configuration Bit 4 T 5 R4 RAM Select RegisterBit Bits 5~0 6 R5 ~ R6 Port 5 ~ Port Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode7 R7 Port Bit 7 ~ Bit 8 R8 Aisr ADC Input Select Register Bit 3 Adpd 9 R9 Adcon ADC Control Register RB Addata Converted Value of ADC RA Adoc ADC Offset Calibration RegisterBit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits Bit 2 ~ Bit 0 Unimplemented, read as ‘0’ RC ADDATA1H Converted Value of ADC RD ADDATA1L Converted Value of ADCRE Interrupt Status 2 & Wake-up Control Register RF Interrupt Status 2 Register 16 R10 ~ R3FAll of these are 8-bit general-purpose registers Special Purpose Registers AccumulatorControl Register 4 IOC80 Comparator and Tcca Control Register 3 IOC50 ~ IOC70 I/O Port Control RegisterBit 7 & Bit 6 Not used Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bits Bit 4 Tccbte Tccb signal edge Bit 6 Tccben Tccb enable bit 0 = disable TccbTccc signal source Bit 0 Tcccte Tccc signal edge IOCA0 IR and Tccc Scale Control Register Bit 2 HF Bit 3 IREBit 1 LGP Bit 0 Iroute IOCC0 Open-Drain Control Register IOCB0 Pull-down Control RegisterBit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60 IOCD0 Pull-high Control Register IOCE0 WDT Control & Interrupt Mask RegistersBit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 = Disable Lpwtif interrupt Lpwtif interrupt enable bit= Enable Lpwtif interrupt IOCF0 Interrupt Mask Register 13 IOC61 Tccb Counter 12 IOC51 Tcca Counter 15 IOC81 Tccc Counter 14 IOC71 TCCBH/MSB Counter 16 IOC91 Low Time Register IOCA1 High Time RegisterIOCB1 High/Low Time Scale Control Register IOCC1 TCC Prescaler Counter Bit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bitsTCC prescaler counter can be read and written to TCC/WDT and Prescaler MUX I/O Ports I/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Reset and Wake-up Operation Reset and Wake-upUsage of Port 5 Input Change Wake-up/Interrupt Function Wake-up Wake-up and Interrupt EM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Following summarizes the initialized values for registers Address Name Reset Type Bit Name Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Tcif Controller Reset Block Diagram Interrupt T and P Status under Status R3 RegisterEvent EM78P259N/260N Interrupt Vector Interrupt Status Priority Reti ADC Control Register AISR/R8, ADCON/R9, ADOC/RA Analog-to-Digital Converter ADC1.1 R8 Aisr ADC Input Select Register Bit 7 ~ Bit 3 ADE3 Bit 2 ADE2 1.2 R9 Adcon AD Control Register P54/TCC/VREF Pin Priority High Medium LowP54 While the CPU is operating = ADC is operatingRA Adoc AD Offset Calibration Register ADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD ADC Operation during Sleep ModeADC Sampling Time AD Conversion Time Programming Process/Considerations Programming ProcessFollow these steps to obtain data from the ADC Define a Control Register Sample Demo Programs Define a General RegisterADC Control Register Define Bits in Adcon AD power on Overview Infrared Remote Control Application/PWM Waveform Generation Fcarrier Function Description IRE Irout Programming the Related Registers IR/PWM Related Status/Data RegistersAddress Name Bit EM78P259N/260N Timer/Counter Under Tcca Counter IOC51Under Tccb Counter IOC61 Under Tccc Counter IOC81 Related Tccx Status/Data Registers Comparator Comparator Output External Reference Signal Using a Comparator as an Operation Amplifier Wake-up from Sleep ModeComparator Interrupt Oscillator Modes OscillatorOscillator Modes Conditions Crystal Oscillator/Ceramic Resonators Crystal Oscillator TypeFrequency C1pF C2pF 18 Serial Mode Crystal/Resonator Circuit Diagram External RC Oscillator Mode Internal Drift Rate RC Frequency Temperature Internal RC Oscillator ModeCext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C 40C ~ +85C 3V~5.5V Total Power-on Considerations External Power-on Reset CircuitProgrammable WDT Time-out Period Vdd Residual Voltage ProtectionEM78P259N EM78P260N Code Option Register Word Code OptionWord Word1 Bit12 ~ Bit0 Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit = Pulses equal to 32/fc s is regarded as signal default = Pulses equal to 8/fc s is regarded as signalBit Microprocessor with OTP ROM Bit 3 HLP Bit 2 ~ 0 PR2 ~ PR0 Protect Bits Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bits Instruction SetCustomer ID Register Word Following are the EM78P259N/260N instruction set Instruction BinaryMnemonic Operation Status Affected Items Rating Absolute Maximum Ratings DC Electrical Characteristics Symbol Parameter Condition Min Typ Max UnitTa=25 C, VDD=5.0V±5%, VSS=0V Voltage Min Typ Max Internal RC Drift Rate Vdd=2.5V to 5.5V, Vss=0V, Ta=25C AD Converter Characteristics Comparator OP Characteristics Device CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C AC Electrical Characteristic Symbol Parameter Conditions Min Typ Max UnitTa=25C, VDD=5V±5%, VSS=0V Reset Timing CLK=0 Timing DiagramsAC Test Input/Output Waveform TCC Input Timing CLKS=0 Package Information Package Type18-Lead Plastic Dual in line Pdip 300 mil Package Type Pin Count Package Size 838 18-Lead Plastic Small Outline SOP 300 mil 650 Lead Plastic Shrink Small Outline Ssop 209 mil Lead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Quality Assurance and Reliability Address Trap DetectTest Category Test Conditions Remarks