Bit Microprocessor with OTP ROM Bit 3 HLP | IBM EM78P259N/260N

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

Bit 3 (HLP):	Power consumption selection
	0 = Low power consumption, applies to working frequency
		at or below 4MHz
	1 = High power consumption, applies to working frequency
		above 4MHz
Bit 2 ~ 0 (PR2 ~ PR0): Protect Bits
	PR2 ~ PR0 are protect bits. Each protect status is as follows:

		PR2			PR1			PR0		Protect
					Others					Enable
		1			1			1		Disable

6.13.2 Code Option Register (Word 1)

Word 1

Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

-

-

RCOUT

NRHL NRE WDTPS CYES

C3

C2

C1

C0 RCM1 RCM0

Bits 12 ~ 11:	Not used (reserved). These bits are set to “1” all the time
Bit 10 (RCOUT):	Instruction clock output enable bit in IRC or ERC mode
	0	= OSCO pin is open drain
	1	= OSCO output instruction clock
Bit 9 (NRHL):	Noise rejection high/low pulses define bit. INT pin is falling or
	rising edge trigger
	0	= Pulses equal to 8/fc [s] is regarded as signal
	1	= Pulses equal to 32/fc [s] is regarded as signal (default)

NOTE

The noise rejection function is turned off under the LXT and sleep mode.

Bit 8 (NRE): Noise rejection enable

0 = disable noise rejection

1 = enable noise rejection (default), but under Low Crystal oscillator (LXT) mode, the noise rejection circuit is always disabled.

68 •	Product Specification (V1.2) 05.18.2007
	(This specification is subject to change without further notice)

Image 74

IBM EM78P259N/260N manual Bit Microprocessor with OTP ROM Bit 3 HLP, Bit 2 ~ 0 PR2 ~ PR0 Protect Bits, Rising edge trigger

Contents

EM78P259N/260N Elan Microelectronics Corporation Contents Analog-To-Digital Converter ADC Reset and Wake-upTCC/WDT and Prescaler 6.1 11.3 11.111.2 11.4 Doc. Version Revision Description Date Bit Microprocessor with OTP ROM FeaturesGeneral Description Pin DIP/SOP Block DiagramPin Assignment Pin DIP/SOP/SSOP EM78P259NP/M Symbol Pin No Type FunctionPin Description EM78P260NP/M/KM 1 R0 Indirect Address Register Function DescriptionOperational Registers 2 R1 Time Clock /Counter EM78P259N/260N Bit Microprocessor with OTP ROM Data Memory Configuration Cont Bit 5 R4 RAM Select RegisterBit 4 T Bits 5~0 7 R7 Port Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode6 R5 ~ R6 Port 5 ~ Port Bit 7 ~ Bit 8 R8 Aisr ADC Input Select Register 9 R9 Adcon ADC Control Register Bit 3 Adpd Bit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits RA Adoc ADC Offset Calibration RegisterRB Addata Converted Value of ADC Bit 2 ~ Bit 0 Unimplemented, read as ‘0’ RE Interrupt Status 2 & Wake-up Control Register RC ADDATA1H Converted Value of ADCRD ADDATA1L Converted Value of ADC All of these are 8-bit general-purpose registers RF Interrupt Status 2 Register16 R10 ~ R3F Control Register Special Purpose RegistersAccumulator Bit 7 & Bit 6 Not used 3 IOC50 ~ IOC70 I/O Port Control Register4 IOC80 Comparator and Tcca Control Register Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bits Tccc signal source Bit 6 Tccben Tccb enable bit 0 = disable TccbBit 4 Tccbte Tccb signal edge Bit 0 Tcccte Tccc signal edge IOCA0 IR and Tccc Scale Control Register Bit 1 LGP Bit 3 IREBit 2 HF Bit 0 Iroute Bit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 IOCB0 Pull-down Control RegisterIOCC0 Open-Drain Control Register Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60 Bit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 IOCD0 Pull-high Control RegisterIOCE0 WDT Control & Interrupt Mask Registers = Enable Lpwtif interrupt Lpwtif interrupt enable bit= Disable Lpwtif interrupt IOCF0 Interrupt Mask Register 12 IOC51 Tcca Counter 13 IOC61 Tccb Counter 14 IOC71 TCCBH/MSB Counter 15 IOC81 Tccc Counter IOCB1 High/Low Time Scale Control Register 16 IOC91 Low Time RegisterIOCA1 High Time Register TCC prescaler counter can be read and written to IOCC1 TCC Prescaler CounterBit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bits TCC/WDT and Prescaler I/O Ports MUX I/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Usage of Port 5 Input Change Wake-up/Interrupt Function Reset and Wake-upReset and Wake-up Operation Wake-up Wake-up and Interrupt EM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Address Name Reset Type Bit Following summarizes the initialized values for registers Name Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Controller Reset Block Diagram Tcif Event InterruptT and P Status under Status R3 Register EM78P259N/260N Reti Interrupt Vector Interrupt Status Priority 1.1 R8 Aisr ADC Input Select Register Analog-to-Digital Converter ADCADC Control Register AISR/R8, ADCON/R9, ADOC/RA Bit 7 ~ Bit 3 ADE3 Bit 2 ADE2 P54 1.2 R9 Adcon AD Control RegisterP54/TCC/VREF Pin Priority High Medium Low RA Adoc AD Offset Calibration Register While the CPU is operating= ADC is operating ADC Sampling Time ADC Operation during Sleep ModeADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD AD Conversion Time Follow these steps to obtain data from the ADC Programming Process/ConsiderationsProgramming Process ADC Control Register Sample Demo Programs Define a General RegisterDefine a Control Register Define Bits in Adcon AD power on Infrared Remote Control Application/PWM Waveform Generation Overview Function Description Fcarrier IRE Irout Address Name Bit Programming the Related RegistersIR/PWM Related Status/Data Registers EM78P259N/260N Under Tccb Counter IOC61 Timer/CounterUnder Tcca Counter IOC51 Under Tccc Counter IOC81 Comparator Related Tccx Status/Data Registers External Reference Signal Comparator Output Comparator Interrupt Using a Comparator as an Operation AmplifierWake-up from Sleep Mode Oscillator Modes OscillatorOscillator Modes Conditions Frequency C1pF C2pF Crystal Oscillator/Ceramic Resonators CrystalOscillator Type External RC Oscillator Mode 18 Serial Mode Crystal/Resonator Circuit Diagram Cext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C Internal RC Oscillator ModeInternal Drift Rate RC Frequency Temperature 40C ~ +85C 3V~5.5V Total Programmable WDT Time-out Period Power-on ConsiderationsExternal Power-on Reset Circuit EM78P259N Residual Voltage ProtectionVdd EM78P260N Word Word1 Bit12 ~ Bit0 Code OptionCode Option Register Word Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit Bit Microprocessor with OTP ROM Bit 3 HLP = Pulses equal to 8/fc s is regarded as signal= Pulses equal to 32/fc s is regarded as signal default Bit 2 ~ 0 PR2 ~ PR0 Protect Bits Customer ID Register Word Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bitsInstruction Set Mnemonic Operation Status Affected Following are the EM78P259N/260N instruction setInstruction Binary Absolute Maximum Ratings Items Rating Ta=25 C, VDD=5.0V±5%, VSS=0V DC Electrical CharacteristicsSymbol Parameter Condition Min Typ Max Unit Internal RC Drift Rate Voltage Min Typ Max AD Converter Characteristics Vdd=2.5V to 5.5V, Vss=0V, Ta=25C Vdd = 5.0V, Vss=0V, Ta=25C Comparator OP CharacteristicsDevice Characteristics Ta=25C, VDD=5V±5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit AC Test Input/Output Waveform Timing DiagramsReset Timing CLK=0 TCC Input Timing CLKS=0 18-Lead Plastic Dual in line Pdip 300 mil Package TypePackage Information Package Type Pin Count Package Size 18-Lead Plastic Small Outline SOP 300 mil 838 Lead Plastic Shrink Small Outline Ssop 209 mil 650 Lead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Test Category Test Conditions Remarks Quality Assurance and ReliabilityAddress Trap Detect