EM78P259N/260N

8-Bit Microprocessor with OTP ROM

6.7.2ADC Data Register (ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD)

When the AD conversion is completed, the result is loaded to the ADDATA, ADDATA1H and ADDATA1L registers. The ADRUN bit is cleared, and the ADIF is set.

6.7.3 ADC Sampling Time

The accuracy, linearity, and speed of the successive approximation of AD converter are dependent on the properties of the ADC and the comparator. The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. The application program controls the length of the sample time to meet the specified accuracy. Generally speaking, the program should wait for 2μs for each KΩ of the analog source impedance and at least 2μs for the low-impedance source. The maximum recommended impedance for analog source is 10KΩ at Vdd=5V. After the analog input channel is selected, this acquisition time must be done before the conversion is started.

6.7.4 AD Conversion Time

CKR1 and CKR0 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU to run at a maximum frequency without sacrificing the AD conversion accuracy. For the EM78P259N/260N, the conversion time per bit is about 4μs. The table below shows the relationship between Tct and the maximum operating frequencies.

CKR1:CKR0

 

Operation

Max. Operation

Max. Conversion

 

Mode

Frequency

Rate/Bit

 

 

Max. Conversion Rate

00

Fosc/16

4 MHz

250kHz (4μs)

15*4μs=60μs (16.7kHz)

01

Fosc/4

1 MHz

250kHz (4μs)

15*4μs=60μs (16.7kHz)

10

Fosc/64

16 MHz

250kHz ( 4μs)

15*4μs=60μs (16.7kHz)

11

Internal RC

14kHz (71μs)

15*71μs=1065μs (0.938kHz)

NOTE

Pin not used as an analog input pin can be used as a regular input or output pin.

During conversion, do not perform output instruction to maintain precision for all of the pins.

6.7.5 ADC Operation during Sleep Mode

In order to obtain a more accurate ADC value and reduce power consumption, the AD conversion remains operational during sleep mode. As the SLEP instruction is executed, all the MCU operations will stop except for the Oscillators TCC, TCCA, TCCB, TCCC and AD conversion.

The AD Conversion is considered completed as determined by:

1.ADRUN bit of R9 register is cleared (“0” value).

2.ADIF bit of RE register is set to “1”.

Product Specification (V1.2) 05.18.2007

• 47

(This specification is subject to change without further notice)

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IBM EM78P259N/260N manual ADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RD, ADC Sampling Time, AD Conversion Time