Programming the Related Registers | IBM EM78P259N/260N manual

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

The following figure shows LGP=1 and HF=1. When this bit is set to high level, the high time segment of the pulse is ignored. So, IROUT waveform output is determined by low time width.

Fcarrier
	low time width	low time width	low time width	high time width
HF	start
	start			IR disable
IRE				IR disable
IRE
IROUT				Always high-level
				Always high-level

Fig. 6-12e LGP=1 and HF=1, IROUT Pin Output Waveform

6.8.3 Programming the Related Registers

When defining IR/PWM, refer to the operation of the related registers as shown in the tables below.

IR/PWM Related Control Registers

	Address	Name	Bit 7	Bit 6	Bit 5	Bit 4		Bit 3

	Bit 2	Bit 1	Bit 0

	0x09	IOC90	TCCBHE/0	TCCBEN/0	TCCBTS/0	TCCBTE/0	0	TCCCEN/0	TCCCTS/0	TCCCTE/0
	0X0A	IR CR	TCCCSE/0	TCCCS2/0	TCCCS1/0	TCCCS0/0	IRE/0	HF/0	LGP/0	IROUTE/0
		/IOCA0

	0x0F	IMR	LPWTIE/0	HPWTIE/0	TCCCIE/0	TCCBIE/0	TCCAIE/0	EXIE/0	ICIE/0	TCIE/0
		/IOCF0

	0X0B	HLTS	HTSE/0	HTS2/0	HTS1/0	HTS0/0	LTSE/0	LTS2/0	LTS1/0	LTS0/0
		/IOCB1

IR/PWM Related Status/Data Registers

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

	0x0F	ISR/RF	LPWTIF/0	HPWTIF/0	TCCCIF/0	TCCBIF/0	TCCAIF/0	EXIF/0	ICIF/0	TCIF/0

	0x06	TCCC	TCCC7/0	TCCC6/0	TCCC5/0	TCCC4/0	TCCC3/0	TCCC2/0	TCCC1/0	TCCC0/0
	0x06	/IOC81	TCCC7/0	TCCC6/0	TCCC5/0	TCCC4/0	TCCC3/0	TCCC2/0	TCCC1/0	TCCC0/0
		/IOC81

	0X09	LTR	LTR7/0	LTR6/0	LTR5/0	LTR4/0	LTR3/0	LTR2/0	LTR1/0	LTR0/0
	0X09	/IOC91	LTR7/0	LTR6/0	LTR5/0	LTR4/0	LTR3/0	LTR2/0	LTR1/0	LTR0/0
		/IOC91

	0X0A	HTR	HTR7/0	HTR6/0	HTR5/0	HTR4/0	HTR3/0	HTR2/0	HTR1/0	HTR0/0
	0X0A	/IOCA1	HTR7/0	HTR6/0	HTR5/0	HTR4/0	HTR3/0	HTR2/0	HTR1/0	HTR0/0
		/IOCA1

54 •	Product Specification (V1.2) 05.18.2007
	(This specification is subject to change without further notice)

Image 60

IBM EM78P259N/260N manual Programming the Related Registers, IR/PWM Related Status/Data Registers, Address Name Bit

Contents

EM78P259N/260N Elan Microelectronics Corporation Contents Reset and Wake-up TCC/WDT and PrescalerAnalog-To-Digital Converter ADC 6.1 11.1 11.211.3 11.4 Doc. Version Revision Description Date Features General DescriptionBit Microprocessor with OTP ROM Block Diagram Pin AssignmentPin DIP/SOP Pin DIP/SOP/SSOP Symbol Pin No Type Function Pin DescriptionEM78P259NP/M EM78P260NP/M/KM Function Description Operational Registers1 R0 Indirect Address Register 2 R1 Time Clock /Counter EM78P259N/260N Bit Microprocessor with OTP ROM Data Memory Configuration Cont 5 R4 RAM Select Register Bit 4 TBit Bits 5~0 Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode 6 R5 ~ R6 Port 5 ~ Port7 R7 Port Bit 7 ~ Bit 8 R8 Aisr ADC Input Select Register 9 R9 Adcon ADC Control Register Bit 3 Adpd RA Adoc ADC Offset Calibration Register RB Addata Converted Value of ADCBit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits Bit 2 ~ Bit 0 Unimplemented, read as ‘0’ RC ADDATA1H Converted Value of ADC RD ADDATA1L Converted Value of ADCRE Interrupt Status 2 & Wake-up Control Register RF Interrupt Status 2 Register 16 R10 ~ R3FAll of these are 8-bit general-purpose registers Special Purpose Registers AccumulatorControl Register 3 IOC50 ~ IOC70 I/O Port Control Register 4 IOC80 Comparator and Tcca Control RegisterBit 7 & Bit 6 Not used Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bits Bit 6 Tccben Tccb enable bit 0 = disable Tccb Bit 4 Tccbte Tccb signal edgeTccc signal source Bit 0 Tcccte Tccc signal edge IOCA0 IR and Tccc Scale Control Register Bit 3 IRE Bit 2 HFBit 1 LGP Bit 0 Iroute IOCB0 Pull-down Control Register IOCC0 Open-Drain Control RegisterBit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60 IOCD0 Pull-high Control Register IOCE0 WDT Control & Interrupt Mask RegistersBit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 Lpwtif interrupt enable bit = Disable Lpwtif interrupt= Enable Lpwtif interrupt IOCF0 Interrupt Mask Register 12 IOC51 Tcca Counter 13 IOC61 Tccb Counter 14 IOC71 TCCBH/MSB Counter 15 IOC81 Tccc Counter 16 IOC91 Low Time Register IOCA1 High Time RegisterIOCB1 High/Low Time Scale Control Register IOCC1 TCC Prescaler Counter Bit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bitsTCC prescaler counter can be read and written to TCC/WDT and Prescaler I/O Ports MUX I/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Reset and Wake-up Reset and Wake-up OperationUsage of Port 5 Input Change Wake-up/Interrupt Function Wake-up Wake-up and Interrupt EM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Address Name Reset Type Bit Following summarizes the initialized values for registers Name Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Controller Reset Block Diagram Tcif Interrupt T and P Status under Status R3 RegisterEvent EM78P259N/260N Reti Interrupt Vector Interrupt Status Priority Analog-to-Digital Converter ADC ADC Control Register AISR/R8, ADCON/R9, ADOC/RA1.1 R8 Aisr ADC Input Select Register Bit 7 ~ Bit 3 ADE3 Bit 2 ADE2 1.2 R9 Adcon AD Control Register P54/TCC/VREF Pin Priority High Medium LowP54 While the CPU is operating = ADC is operatingRA Adoc AD Offset Calibration Register ADC Operation during Sleep Mode ADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RDADC Sampling Time AD Conversion Time Programming Process/Considerations Programming ProcessFollow these steps to obtain data from the ADC Sample Demo Programs Define a General Register Define a Control RegisterADC Control Register Define Bits in Adcon AD power on Infrared Remote Control Application/PWM Waveform Generation Overview Function Description Fcarrier IRE Irout Programming the Related Registers IR/PWM Related Status/Data RegistersAddress Name Bit EM78P259N/260N Timer/Counter Under Tcca Counter IOC51Under Tccb Counter IOC61 Under Tccc Counter IOC81 Comparator Related Tccx Status/Data Registers External Reference Signal Comparator Output Using a Comparator as an Operation Amplifier Wake-up from Sleep ModeComparator Interrupt Oscillator Oscillator ModesOscillator Modes Conditions Crystal Oscillator/Ceramic Resonators Crystal Oscillator TypeFrequency C1pF C2pF External RC Oscillator Mode 18 Serial Mode Crystal/Resonator Circuit Diagram Internal RC Oscillator Mode Internal Drift Rate RC Frequency TemperatureCext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C 40C ~ +85C 3V~5.5V Total Power-on Considerations External Power-on Reset CircuitProgrammable WDT Time-out Period Residual Voltage Protection VddEM78P259N EM78P260N Code Option Code Option Register WordWord Word1 Bit12 ~ Bit0 Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit = Pulses equal to 8/fc s is regarded as signal = Pulses equal to 32/fc s is regarded as signal defaultBit Microprocessor with OTP ROM Bit 3 HLP Bit 2 ~ 0 PR2 ~ PR0 Protect Bits Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bits Instruction SetCustomer ID Register Word Following are the EM78P259N/260N instruction set Instruction BinaryMnemonic Operation Status Affected Absolute Maximum Ratings Items Rating DC Electrical Characteristics Symbol Parameter Condition Min Typ Max UnitTa=25 C, VDD=5.0V±5%, VSS=0V Internal RC Drift Rate Voltage Min Typ Max AD Converter Characteristics Vdd=2.5V to 5.5V, Vss=0V, Ta=25C Comparator OP Characteristics Device CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C AC Electrical Characteristic Symbol Parameter Conditions Min Typ Max UnitTa=25C, VDD=5V±5%, VSS=0V Timing Diagrams Reset Timing CLK=0AC Test Input/Output Waveform TCC Input Timing CLKS=0 Package Type Package Information18-Lead Plastic Dual in line Pdip 300 mil Package Type Pin Count Package Size 18-Lead Plastic Small Outline SOP 300 mil 838 Lead Plastic Shrink Small Outline Ssop 209 mil 650 Lead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Quality Assurance and Reliability Address Trap DetectTest Category Test Conditions Remarks