Manuals / IBM / Computer Equipment / Network Card

IBM manual Following are the EM78P259N/260N instruction set, Instruction Binary

Models: EM78P259N/260N

1 89

Download 89 pages 38.24 Kb

Page 76

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

Convention:

R = Register designator that specifies which one of the registers (including operation and general purpose registers) is to be utilized by the instruction.

b = Bit field designator that selects the value for the bit located in the register R and which affects the operation.

k = 8 or 10-bit constant or literal value

The following are the EM78P259N/260N instruction set

	Instruction Binary				HEX	Mnemonic	Operation	Status Affected


	0	0000	0000 0000		0000	NOP	No Operation	None
	0	0000	0000 0001		0001	DAA	Decimal Adjust A	C
	0	0000	0000 0010		0002	CONTW	A → CONT	None
	0	0000	0000 0011		0003	SLEP	0 → WDT, Stop oscillator	T, P
	0	0000	0000 0100		0004	WDTC	0 → WDT	T, P
	0	0000	0000 rrrr		000r	IOW R	A → IOCR	None1
	0	0000	0001 0000		0010	ENI	Enable Interrupt	None
	0	0000	0001	0001	0011	DISI	Disable Interrupt	None
	0	0000	0001 0010		0012	RET	[Top of Stack] → PC	None
	0	0000	0001 0011		0013	RETI	[Top of Stack] → PC, Enable Interrupt	None
	0	0000	0001 0100		0014	CONTR	CONT → A	None
	0	0000	0001 rrrr		001r	IOR R	IOCR → A	None1
	0	0000	01rr	rrrr	00rr	MOV R,A	A → R	None
	0	0000	1000 0000		0080	CLRA	0 → A	Z
	0	0000	11rr	rrrr	00rr	CLR R	0 → R	Z
	0	0001	00rr	rrrr	01rr	SUB A,R	R-A → A	Z, C, DC
	0	0001	01rr	rrrr	01rr	SUB R,A	R-A → R	Z, C, DC
	0	0001	10rr	rrrr	01rr	DECA R	R-1 → A	Z
	0	0001	11rr	rrrr	01rr	DEC R	R-1 → R	Z
	0	0010	00rr	rrrr	02rr	OR A,R	A ∨ VR → A	Z
	0	0010	01rr	rrrr	02rr	OR R,A	A ∨ VR → R	Z
	0	0010	10rr	rrrr	02rr	AND A,R	A & R → A	Z
	0	0010	11rr	rrrr	02rr	AND R,A	A & R → R	Z
	0	0011	00rr	rrrr	03rr	XOR A,R	A ⊕ R → A	Z
	0	0011	01rr	rrrr	03rr	XOR R,A	A ⊕ R → R	Z
	0	0011	10rr	rrrr	03rr	ADD A,R	A + R → A	Z, C, DC
	0	0011	11rr	rrrr	03rr	ADD R,A	A + R → R	Z, C, DC
	0	0100	00rr	rrrr	04rr	MOV A,R	R → A	Z
	0	0100	01rr	rrrr	04rr	MOV R,R	R → R	Z
	0	0100	10rr	rrrr	04rr	COMA R	/R → A	Z
	0	0100	11rr	rrrr	04rr	COM R	/R → R	Z
	0	0101	00rr	rrrr	05rr	INCA R	R+1 → A	Z

70 •							Product Specification (V1.2) 05.18.2007
							(This specification is subject to change without further notice)

Image 76

IBM manual Following are the EM78P259N/260N instruction set, Instruction Binary, Mnemonic Operation Status Affected

Contents

EM78P259N/260N Elan Microelectronics Corporation Contents Reset and Wake-up TCC/WDT and PrescalerAnalog-To-Digital Converter ADC 6.111.1 11.211.3 11.4Doc. Version Revision Description DateGeneral Description FeaturesBit Microprocessor with OTP ROM Block Diagram Pin AssignmentPin DIP/SOP Pin DIP/SOP/SSOPPin Description Symbol Pin No Type FunctionEM78P259NP/M EM78P260NP/M/KM Function Description Operational Registers1 R0 Indirect Address Register 2 R1 Time Clock /CounterEM78P259N/260N Bit Microprocessor with OTP ROM Data Memory Configuration Cont5 R4 RAM Select Register Bit 4 TBit Bits 5~0Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode 6 R5 ~ R6 Port 5 ~ Port7 R7 Port Bit 7 ~ Bit8 R8 Aisr ADC Input Select Register 9 R9 Adcon ADC Control Register Bit 3 AdpdRA Adoc ADC Offset Calibration Register RB Addata Converted Value of ADCBit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits Bit 2 ~ Bit 0 Unimplemented, read as ‘0’RD ADDATA1L Converted Value of ADC RC ADDATA1H Converted Value of ADCRE Interrupt Status 2 & Wake-up Control Register 16 R10 ~ R3F RF Interrupt Status 2 RegisterAll of these are 8-bit general-purpose registers Accumulator Special Purpose RegistersControl Register 3 IOC50 ~ IOC70 I/O Port Control Register 4 IOC80 Comparator and Tcca Control RegisterBit 7 & Bit 6 Not used Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bitsBit 6 Tccben Tccb enable bit 0 = disable Tccb Bit 4 Tccbte Tccb signal edgeTccc signal source Bit 0 Tcccte Tccc signal edgeIOCA0 IR and Tccc Scale Control Register Bit 3 IRE Bit 2 HFBit 1 LGP Bit 0 IrouteIOCB0 Pull-down Control Register IOCC0 Open-Drain Control RegisterBit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60IOCE0 WDT Control & Interrupt Mask Registers IOCD0 Pull-high Control RegisterBit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 Lpwtif interrupt enable bit = Disable Lpwtif interrupt= Enable Lpwtif interrupt IOCF0 Interrupt Mask Register12 IOC51 Tcca Counter 13 IOC61 Tccb Counter14 IOC71 TCCBH/MSB Counter 15 IOC81 Tccc CounterIOCA1 High Time Register 16 IOC91 Low Time RegisterIOCB1 High/Low Time Scale Control Register Bit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bits IOCC1 TCC Prescaler CounterTCC prescaler counter can be read and written to TCC/WDT and Prescaler I/O Ports MUXI/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Reset and Wake-up Reset and Wake-up OperationUsage of Port 5 Input Change Wake-up/Interrupt Function Wake-up Wake-up and InterruptEM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Address Name Reset Type Bit Following summarizes the initialized values for registersName Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Controller Reset Block Diagram TcifT and P Status under Status R3 Register InterruptEvent EM78P259N/260N Reti Interrupt Vector Interrupt Status PriorityAnalog-to-Digital Converter ADC ADC Control Register AISR/R8, ADCON/R9, ADOC/RA1.1 R8 Aisr ADC Input Select Register Bit 7 ~ Bit 3 ADE3 Bit 2 ADE2P54/TCC/VREF Pin Priority High Medium Low 1.2 R9 Adcon AD Control RegisterP54 = ADC is operating While the CPU is operatingRA Adoc AD Offset Calibration Register ADC Operation during Sleep Mode ADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RDADC Sampling Time AD Conversion TimeProgramming Process Programming Process/ConsiderationsFollow these steps to obtain data from the ADC Sample Demo Programs Define a General Register Define a Control RegisterADC Control Register Define Bits in AdconAD power on Infrared Remote Control Application/PWM Waveform Generation OverviewFunction Description FcarrierIRE Irout IR/PWM Related Status/Data Registers Programming the Related RegistersAddress Name Bit EM78P259N/260N Under Tcca Counter IOC51 Timer/CounterUnder Tccb Counter IOC61 Under Tccc Counter IOC81 Comparator Related Tccx Status/Data RegistersExternal Reference Signal Comparator OutputWake-up from Sleep Mode Using a Comparator as an Operation AmplifierComparator Interrupt Oscillator Oscillator ModesOscillator Modes ConditionsOscillator Type Crystal Oscillator/Ceramic Resonators CrystalFrequency C1pF C2pF External RC Oscillator Mode 18 Serial Mode Crystal/Resonator Circuit DiagramInternal RC Oscillator Mode Internal Drift Rate RC Frequency TemperatureCext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C 40C ~ +85C 3V~5.5V TotalExternal Power-on Reset Circuit Power-on ConsiderationsProgrammable WDT Time-out Period Residual Voltage Protection VddEM78P259N EM78P260NCode Option Code Option Register WordWord Word1 Bit12 ~ Bit0 Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit= Pulses equal to 8/fc s is regarded as signal = Pulses equal to 32/fc s is regarded as signal defaultBit Microprocessor with OTP ROM Bit 3 HLP Bit 2 ~ 0 PR2 ~ PR0 Protect BitsInstruction Set Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bitsCustomer ID Register Word Instruction Binary Following are the EM78P259N/260N instruction setMnemonic Operation Status Affected Absolute Maximum Ratings Items RatingSymbol Parameter Condition Min Typ Max Unit DC Electrical CharacteristicsTa=25 C, VDD=5.0V±5%, VSS=0V Internal RC Drift Rate Voltage Min Typ MaxAD Converter Characteristics Vdd=2.5V to 5.5V, Vss=0V, Ta=25CDevice Characteristics Comparator OP CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C Symbol Parameter Conditions Min Typ Max Unit AC Electrical CharacteristicTa=25C, VDD=5V±5%, VSS=0V Timing Diagrams Reset Timing CLK=0AC Test Input/Output Waveform TCC Input Timing CLKS=0Package Type Package Information18-Lead Plastic Dual in line Pdip 300 mil Package Type Pin Count Package Size18-Lead Plastic Small Outline SOP 300 mil 838Lead Plastic Shrink Small Outline Ssop 209 mil 650Lead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Address Trap Detect Quality Assurance and ReliabilityTest Category Test Conditions Remarks