IOCF0 Interrupt Mask Register | IBM EM78P259N/260N specs

EM78P259N/260N

8-Bit Microprocessor with OTP ROM

Bit 5 (ADIE): ADIF interrupt enable bit 0 = disable ADIF interrupt 1 = enable ADIF interrupt

Bit 4 (CMPIE): CMPIF interrupt enable bit. 0 = disable CMPIF interrupt 1 = enable CMPIF interrupt

Bit 3 (PSWE): Prescaler enable bit for WDT

0 = prescaler disable bit, WDT rate is 1:1

1 = prescaler enable bit, WDT rate is set as Bit 2 ~ Bit 0 Bit 2 ~ Bit 0 (PSW2 ~ PSW0): WDT prescaler bits

PSW2 PSW1 PSW0 WDT Rate

0	0	0

0	0	1

0	1	0

0	1	1

1	0	0

1	0	1

1	1	0

1	1	1

1:2

1:4

1:8

1:16

1:32

1:64

1:128

1:256

6.2.11 IOCF0 (Interrupt Mask Register)

	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
	LPWTIE	HPWTIE	TCCCIE	TCCBIE	TCCAIE	EXIE	ICIE	TCIE

NOTE

■The IOCF0 register is both readable and writable

■Individual interrupt is enabled by setting its associated control bit in the IOCF0 and in IOCE0 Bit 4 & 5 to "1".

■Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).

Bit 7	(LPWTIE):	LPWTIF interrupt enable bit
		0	= Disable LPWTIF interrupt
		1	= Enable LPWTIF interrupt
Bit 6	(HPWTIE): HPWTIF interrupt enable bit
		0	= Disable HPWTIF interrupt
		1	= Enable HPWTIF interrupt

22 •			Product Specification (V1.2) 05.18.2007
			(This specification is subject to change without further notice)

Image 28

IBM EM78P259N/260N manual IOCF0 Interrupt Mask Register, Lpwtif interrupt enable bit, = Disable Lpwtif interrupt

Contents

EM78P259N/260N Elan Microelectronics Corporation Contents Reset and Wake-up TCC/WDT and PrescalerAnalog-To-Digital Converter ADC 6.1 11.1 11.211.3 11.4 Doc. Version Revision Description Date General Description FeaturesBit Microprocessor with OTP ROM Block Diagram Pin AssignmentPin DIP/SOP Pin DIP/SOP/SSOP Pin Description Symbol Pin No Type FunctionEM78P259NP/M EM78P260NP/M/KM Function Description Operational Registers1 R0 Indirect Address Register 2 R1 Time Clock /Counter EM78P259N/260N Bit Microprocessor with OTP ROM Data Memory Configuration Cont 5 R4 RAM Select Register Bit 4 TBit Bits 5~0 Bit 7 ~ Bit 4 C3 ~ C0 Calibrator of internal RC mode 6 R5 ~ R6 Port 5 ~ Port7 R7 Port Bit 7 ~ Bit 8 R8 Aisr ADC Input Select Register 9 R9 Adcon ADC Control Register Bit 3 Adpd RA Adoc ADC Offset Calibration Register RB Addata Converted Value of ADCBit 5 ~ Bit 3 VOF2 ~ VOF0 Offset voltage bits Bit 2 ~ Bit 0 Unimplemented, read as ‘0’ RD ADDATA1L Converted Value of ADC RC ADDATA1H Converted Value of ADCRE Interrupt Status 2 & Wake-up Control Register 16 R10 ~ R3F RF Interrupt Status 2 RegisterAll of these are 8-bit general-purpose registers Accumulator Special Purpose RegistersControl Register 3 IOC50 ~ IOC70 I/O Port Control Register 4 IOC80 Comparator and Tcca Control RegisterBit 7 & Bit 6 Not used Bit 4 & Bit 3 COS1 & COS0 Comparator/OP Select bits Bit 6 Tccben Tccb enable bit 0 = disable Tccb Bit 4 Tccbte Tccb signal edgeTccc signal source Bit 0 Tcccte Tccc signal edge IOCA0 IR and Tccc Scale Control Register Bit 3 IRE Bit 2 HFBit 1 LGP Bit 0 Iroute IOCB0 Pull-down Control Register IOCC0 Open-Drain Control RegisterBit PD57 PD56 PD55 PD54 PD53 PD52 PD51 PD50 Bit OD67 OD66 OD65 OD64 OD63 OD62 OD61 OD60 IOCE0 WDT Control & Interrupt Mask Registers IOCD0 Pull-high Control RegisterBit PH57 PH56 PH55 PH54 PH53 PH52 PH51 PH50 Lpwtif interrupt enable bit = Disable Lpwtif interrupt= Enable Lpwtif interrupt IOCF0 Interrupt Mask Register 12 IOC51 Tcca Counter 13 IOC61 Tccb Counter 14 IOC71 TCCBH/MSB Counter 15 IOC81 Tccc Counter IOCA1 High Time Register 16 IOC91 Low Time RegisterIOCB1 High/Low Time Scale Control Register Bit 2 ~ Bit 0 LTS2 ~ LTS0 Low time scale bits IOCC1 TCC Prescaler CounterTCC prescaler counter can be read and written to TCC/WDT and Prescaler I/O Ports MUX I/O Port and I/O Control Register Circuit for P60 /INT I/O Port and I/O Control Register Circuit for Port 50 ~ P57 Reset and Wake-up Reset and Wake-up OperationUsage of Port 5 Input Change Wake-up/Interrupt Function Wake-up Wake-up and Interrupt EM78P259N/260N Select Segment Signal Sleep Mode Normal Mode Comparator Address Name Reset Type Bit Following summarizes the initialized values for registers Name Reset Type Bit HTR7 HTR6 HTR5 HTR4 HTR3 HTR2 HTR1 HTR0 Aisr Controller Reset Block Diagram Tcif T and P Status under Status R3 Register InterruptEvent EM78P259N/260N Reti Interrupt Vector Interrupt Status Priority Analog-to-Digital Converter ADC ADC Control Register AISR/R8, ADCON/R9, ADOC/RA1.1 R8 Aisr ADC Input Select Register Bit 7 ~ Bit 3 ADE3 Bit 2 ADE2 P54/TCC/VREF Pin Priority High Medium Low 1.2 R9 Adcon AD Control RegisterP54 = ADC is operating While the CPU is operatingRA Adoc AD Offset Calibration Register ADC Operation during Sleep Mode ADC Data Register ADDATA/RB, ADDATA1H/RC, ADDATA1L/RDADC Sampling Time AD Conversion Time Programming Process Programming Process/ConsiderationsFollow these steps to obtain data from the ADC Sample Demo Programs Define a General Register Define a Control RegisterADC Control Register Define Bits in Adcon AD power on Infrared Remote Control Application/PWM Waveform Generation Overview Function Description Fcarrier IRE Irout IR/PWM Related Status/Data Registers Programming the Related RegistersAddress Name Bit EM78P259N/260N Under Tcca Counter IOC51 Timer/CounterUnder Tccb Counter IOC61 Under Tccc Counter IOC81 Comparator Related Tccx Status/Data Registers External Reference Signal Comparator Output Wake-up from Sleep Mode Using a Comparator as an Operation AmplifierComparator Interrupt Oscillator Oscillator ModesOscillator Modes Conditions Oscillator Type Crystal Oscillator/Ceramic Resonators CrystalFrequency C1pF C2pF External RC Oscillator Mode 18 Serial Mode Crystal/Resonator Circuit Diagram Internal RC Oscillator Mode Internal Drift Rate RC Frequency TemperatureCext Rext Average Fosc 5V, 25C Average Fosc 3V, 25C 40C ~ +85C 3V~5.5V Total External Power-on Reset Circuit Power-on ConsiderationsProgrammable WDT Time-out Period Residual Voltage Protection VddEM78P259N EM78P260N Code Option Code Option Register WordWord Word1 Bit12 ~ Bit0 Word Bit Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit = Pulses equal to 8/fc s is regarded as signal = Pulses equal to 32/fc s is regarded as signal defaultBit Microprocessor with OTP ROM Bit 3 HLP Bit 2 ~ 0 PR2 ~ PR0 Protect Bits Instruction Set Bit 1 & Bit 0 RCM1, RCM0 RC mode selection bitsCustomer ID Register Word Instruction Binary Following are the EM78P259N/260N instruction setMnemonic Operation Status Affected Absolute Maximum Ratings Items Rating Symbol Parameter Condition Min Typ Max Unit DC Electrical CharacteristicsTa=25 C, VDD=5.0V±5%, VSS=0V Internal RC Drift Rate Voltage Min Typ Max AD Converter Characteristics Vdd=2.5V to 5.5V, Vss=0V, Ta=25C Device Characteristics Comparator OP CharacteristicsVdd = 5.0V, Vss=0V, Ta=25C Symbol Parameter Conditions Min Typ Max Unit AC Electrical CharacteristicTa=25C, VDD=5V±5%, VSS=0V Timing Diagrams Reset Timing CLK=0AC Test Input/Output Waveform TCC Input Timing CLKS=0 Package Type Package Information18-Lead Plastic Dual in line Pdip 300 mil Package Type Pin Count Package Size 18-Lead Plastic Small Outline SOP 300 mil 838 Lead Plastic Shrink Small Outline Ssop 209 mil 650 Lead Plastic Dual-in-line Pdip 300 mil Lead Plastic Small Outline SOP 300 mil Address Trap Detect Quality Assurance and ReliabilityTest Category Test Conditions Remarks