EM78P259N/260N

8-Bit Microprocessor with OTP ROM

1CLK (Fosc/1)

2 CLK (Fosc/2)

 

 

 

0

8-Bit Counter (IOCC1)

Data Bus

 

 

TCC Pin

MUX

 

 

1

 

 

TE (CONT)

 

8 to 1 MUX

TCC (R1)

 

TS (CONT)

Prescaler

 

 

 

TCCoverflow

 

 

 

 

 

 

interrupt

 

 

PSR2~0

 

WDT

8-Bit counter

(CONT)

 

 

 

WDTE

8 to 1 MUX

Prescaler

 

 

 

 

(IOCE0)

 

 

 

 

WDT Time out

PSW2~0

 

 

(IOCE0)

 

 

 

 

Fig. 6-2 TCC and WDT Block Diagram

6.4 I/O Ports

The I/O registers (Port 5, Port 6, and Port 7) are bi-directional tri-state I/O ports. Port 5 is pulled-high and pulled-down internally by software. Likewise, P6 has its open-drain output through software. Port 5 features an input status changed interrupt (or wake-up) function. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5, Port 6, and Port7 are illustrated in Figures 6-3, 6-4, 6-5, & 6-6 (see next page).

28 •

Product Specification (V1.2) 05.18.2007

(This specification is subject to change without further notice)

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Image 34
IBM EM78P259N/260N manual I/O Ports, Mux