EM78P259N/260N
8-Bit Microprocessor with OTP ROM
Product Specification (V1.2) 05.18.2007 23
(This specification is subject to change without further notice)
Bit 5 (TCCCIE): TCCCIF interrupt enable bit
0 = Disable TCCCIF interrupt
1 = Enable TCCCIF interrupt
Bit 4 (TCCBIE): TCCBIF interrupt enable bit
0 = Disable TCCBIF interrupt
1 = Enable TCCBIF interrupt
Bit 3 (TCCAIE): TCCAI F interrupt enable bit
0 = Disable TCCAIF interrupt
1 = Enable TCCAIF interrupt
Bit 2 (EXIE): EXIF interrupt enable bit
0 = Disable EXIF interrupt
1 = Enable EXIF interrupt
Bit 1 (ICIE): ICIF interrupt enable bit
0 = Disable ICIF interrupt
1 = Enable ICIF interrupt
Bit 0 (TCIE): TCIF interrupt enable bit.
0 = Disable TCIF interrupt
1 = Enable TCIF interrupt
6.2.12 IOC51 (TCCA Counter)
The IOC51 (TCCA) is an 8-bit clock counter. It can be read, written, and cleared on
any reset condition and is an Up Counter.
NOTE
TCCA timeout period [1/Fosc x (256-TCCA cnt) x 1(CLK=2)]
TCCA timeout period [1/Fosc x (256-TCCA cnt) x 2(CLK=4)]
6.2.13 IOC61 (TCCB Counter)
The IOC61 (TCCB) is an 8-bit clock counter for the least significant byte of TCCBX
(TCCB). It can be read, written, and cleared on any reset condition and is an Up
Counter.