IBM EM78P447N manual Operational Registers, 4.1.1 R0 Indirect Addressing Register

Models: EM78P447N

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4.1 Operational Registers

EM78P447N

8-Bit Microcontroller with OTP ROM

4.1 Operational Registers

4.1.1 R0 (Indirect Addressing Register)

R0 is not a physically implemented register. Its major function is to act as an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4).

4.1.2 R1 (Time Clock /Counter)

Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock.

Writable and readable as any other registers.

Defined by resetting PAB (CONT-3).

The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.

The contents of the prescaler counter will be cleared only when TCC register is written a value.

4.1.3 R2 (Program Counter) & Stack

Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in Fig.3.

Generating 102413 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long.

R2 is set as all "0"s when under RESET condition.

"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page.

"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page.

"RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level stack.

"ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits of the PC are cleared.

"MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC are cleared.

Any instruction that writes to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of a page.

Product Specification (V1.1) 03.30.2005

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(This specification is subject to change without further notice)

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IBM EM78P447N manual Operational Registers, 4.1.1 R0 Indirect Addressing Register, 4.1.2 R1 Time Clock /Counter