EM78P447N
4.12 Instruction Set
Each instruction in the instruction set is a
If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows:
(A)Change one instruction cycle to consist of 4 oscillator periods.
(B)Executed within two instruction cycles, "JMP", "CALL", "RET", "RETL", "RETI", or the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") instructions which were tested to be true. Also execute within two instruction cycles, the instructions that are written to the program counter.
Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high.
Note that once the 4 oscillator periods within one instruction cycle is selected as in Case (A), the internal clock source to TCC should be CLK=Fosc/4, not Fosc/ 2 as indicated in Fig. 5.
In addition, the instruction set has the following features:
(1)Every bit of any register can be set, cleared, or tested directly.
(2)The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register.
The symbol "R" represents a register designator that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. "b" represents a bit field designator that selects the value for the bit which is located in the register "R", and affects operation. "k" represents an 8 or
30 • | Product Specification (V1.1) 03.30.2005 |
(This specification is subject to change without further notice)