EM78P447N
4.5 RESET and Wake-up
4.5.1 RESET
A RESET is initiated by one of the following events-
(1)Power on reset, or
(2)/RESET pin input “low”, or
(3)WDT timeout. (if enabled)
The device is kept in a RESET condition for a period of approx. 18ms3 (one oscillator
The oscillator starts or is running
The Program Counter (R2) is set to all "1".
When power is switched on, bits 5~6 of R3 and the upper 2 bits of R4 are cleared.
All I/O port pins are configured as input mode
The Watchdog timer and prescaler are cleared.
Upon power on, the bits 5~6 of R3 are cleared.
Upon power on, the upper 2 bits of R4 are cleared.
The bits of CONT register are set to all "1" except bit 6 (INT flag).
IOCB register is set to ”1” (disable P60 ~ P67
Bits 3 and 6 of IOCE register are cleared, and Bits 0, 4, and 5 are set to "1".
Bits 0 and 3 of R3F register and Bits 0 and 3 of IOCF registers are cleared.
The sleep (power down) mode is asserted by executing the “SLEP” instruction. While entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by-
(1)External reset input on /RESET pin;
(2)WDT
The above two cases will cause the controller EM78P447N to reset. The T and P flags of R3 can be used to determine the source of the reset
In addition to the basic SLEEP1 MODE, EM78P447N has another sleep mode (designated as SLEEP2 MODE and is invoked by clearing the IOCE register “SLPC” bit). In the SLEEP2 MODE, the controller can be awakened by-
3NOTE: Vdd = 5V, set up time period = 16.2ms ± 30% Vdd = 3V, set up time period = 19.6ms ± 30%
Product Specification (V1.1) 03.30.2005 | • 17 |
(This specification is subject to change without further notice)