MPCMM0002 CMM—Rear Connections

Table 11.

Data Connector Pinouts (Sheet 2 of 2)

 

 

 

 

 

 

 

Signal Name

 

Count

Type

Description

Pin Name From Table 12

 

 

 

 

 

 

CFG_STX

 

1

O

Serial transmit

A28

 

 

 

 

 

 

CFG_SRX

 

1

I

Serial receive

D28

 

 

 

 

 

 

CFG_SCTS

 

1

I

Serial clear to send

E28

 

 

 

 

 

 

CFG_SRTS

 

1

O

Serial request to send

C28

 

 

 

 

 

 

CFG_SDSR

 

1

I

Serial data set ready

E29

 

 

 

 

 

 

CFG_SDTR

 

1

O

Serial data terminal ready

B28

 

 

 

 

 

BP_CMC_TX0(+-)

2

I/O

Ethernet port 0 to switch

A41, B41

 

 

 

 

 

BP_CMC_RX0(+-)

2

I/O

Ethernet port 0 from switch

A43, B43

 

 

 

 

 

BP_CMCX_TX0(+-)

2

I/O

Ethernet port 1 to switch

A45, B45

 

 

 

 

 

BP_CMCX_RX0(+-)

2

I/O

Ethernet port 1 from switch

A 47, B47

 

 

 

 

 

BP_CMC_TX1(+-)

2

I/O

Reserved for GbE to switch

D41, E41

 

 

 

 

 

BP_CMC_RX1(+-)

2

I/O

Reserved for GbE from switch

D43, E43

 

 

 

 

 

BP_CMCX_TX1(+-)

2

I/O

Reserved for GbE to switch

D45, E45

 

 

 

 

 

BP_CMCX_RX1(+-)

2

I/O

Reserved for GbE from switch

D47, E47

 

 

 

 

 

 

BP_NGO

 

1

O

Negotiate output to other CMM

E14

 

 

 

 

 

 

BP_NGOI

 

1

I

Negotiate input from other CMM

E15

 

 

 

 

 

 

BP_HLY#

 

1

O

Healthy output to other CMM

E12

 

 

 

 

 

 

BP_HLYI#

 

1

I

Healthy input from other CMM

E13

 

 

 

 

 

 

BP_PRESI#

 

1

I

Other CMM is present (0V)

E11

 

 

 

 

 

 

BP_PRES#

 

1

O

Tie to ground

E10

 

 

 

 

 

 

GA[0:7]

 

8

I

Hardware Address

E2-E9

 

 

 

 

 

 

 

 

 

 

 

A1-E1, A23-C23, A32-E32,

GND

 

61

I

Ground

C33, A34-E34, C35, A36-E36,

 

C37, A38-E38, C39, A40-E40,

 

 

 

 

 

C41, A42-E42, C43, A44-E44,

 

 

 

 

 

C45, A46-E46, C47, A48-E48

 

 

 

 

 

 

FRU_VCCA and B

 

2

I

Power to CDMs (shelf FRUs) and distribution

E22, E23

 

board

 

 

 

 

 

 

 

 

 

 

 

RESV[1:11]

 

11

 

Reserved

A26-E26, A27-E27, D23

 

 

 

 

 

 

GPIO[1:10]

 

10

I

General Purpose Input Only

A24-E24, A25-E25

 

 

 

 

 

BP_CMM_RESET#

1

O

Inter CMM reset output to another CMM

C29

 

 

 

 

 

BP_CMM_RESETI#

1

I

Inter CMM reset input from another CMM

D29

 

 

 

 

 

 

 

Table 12 identifies each pin on the data connector at the intersection of each row (A-E)

 

and column (1-48).

 

 

Table 12.

Data Connector Pinouts Matrix (Sheet 1 of 3)

 

 

 

 

 

 

 

 

 

 

 

E

D

C

B

A

 

 

 

 

 

 

 

1

GND

 

GND

GND

GND

GND

 

 

 

 

 

 

 

2

GA0

 

BP_N_SDA_[1]_B

BP_N_SCL_[1]_B

BP_N_SDA_[1]_A

BP_N_SCL_[1]_A

 

 

 

 

 

 

 

3

GA1

 

BP_N_SDA_[2]_B

BP_N_SCL_[2]_B

BP_N_SDA_[2]_A

BP_N_SCL_[2]_A

 

 

 

 

 

 

 

4

GA2

 

BP_N_SDA_[3]_B

BP_N_SCL_[3]_B

BP_N_SDA_[3]_A

BP_N_SCL_[3]_A

 

 

 

 

 

 

 

Intel NetStructure® MPCMM0002 Chassis Management Module

 

Hardware TPS

July 2007

38

Order Number: 309247-004US

Page 37
Image 37
Intel MPCMM0002 manual Data Connector Pinouts Sheet 2, Data Connector Pinouts Matrix Sheet 1