MPCMM0002
Table 7 labels the pins on the power connector at the intersection of each row
Table 7. | Power Connector Pinouts Matrix |
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| E | D | C | B | A |
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| 1 |
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| 4 |
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| 5 | GND |
| GND |
| GND |
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| 6 |
| PWRALRM_NO |
| PWRALRM_COM |
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| 7 | MNR_NO |
| MJR_NO |
| CRT_NO |
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| 8 |
| MJR+ |
| MJR- |
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| 9 | MNR_COM |
| MJR_COM |
| CRT_COM |
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| 10 |
| MNR+ |
| MNR- |
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| 11 | MNR_NC |
| MJR_NC |
| CRT_NC |
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| 12 |
| SGND |
| SGND |
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Table 8 shows the staging of the power connector pins. Table 9 and Table 10 (for the receptacle and for the header) show the physical locations of the pins identified by pin code.
Table 8. | Pin Staging |
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| Order | Mating | Tail | Pin Code |
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| First Mate | 8 mm | 4.3mm | 19 |
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| Second Mate | 7.25 mm | 4.3mm | 4 |
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| Third Mate | 6.5 mm | 4.3mm | 3 |
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| Fourth Mate | 5.75 mm | 4.3mm | 2 |
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| Last Mate | 5 mm | 4.3mm | 1 |
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| Empty |
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Table 9. | Power Connector Receptacle Pin Placement (Sheet 1 of 2) |
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| E | D | C | B | A |
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| 1 | 4 |
| 4 |
| 1 |
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| 3 |
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| 3 | 4 |
| 4 |
| 1 |
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| 4 |
| 3 |
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Intel NetStructure® MPCMM0002 Chassis Management Module |
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Hardware TPS | July 2007 |
34 | Order Number: |