Program Memory Write Procedure, VDD+1 | NEC PD75P308 specification

μPD75P308

3.2 PROGRAM MEMORY WRITE PROCEDURE

The program memory write procedure is as follows. High-speed program memory write is possible.

(1)Ground the unused pins through pull-down resistors. The X1 pin must be low.

(2)Supply 5 V to the VDD and VPP pins.

(3)Wait for 10 microseconds.

(4)Set program memory address 0 clear mode.

(5)Supply 6 V to the VDD pin and 12.5 V to the VPP pin.

(6)Set program inhibit mode.

(7)Write data in 1-millisecond write mode.

(8)Set program inhibit mode.

(9)Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been written, repeat steps (7) to (9).

(10)Write additional data for (the number of times data was written (X) in steps (7) to (9)) times

1milliseconds.

(11)Set program inhibit mode.

(12)Supply a pulse to the X1 pin four times to update the program memory address by 1.

(13)Repeat steps (7) to (12) to the last address.

(14)Set program memory address 0 clear mode.

(15)Change the voltages of VDD and VPP pins to 5 V.

(16)Turn off the power supply.

Steps (2) to (12) are illustrated below.

X-time repetition

Write Verify Additional data write

Address

increment

VPP

VPP

VDD

VDD+1

VDD	VDD
	VDD
	X1
P40-P43		Data	Data input
	Data input	output	Data input
P50-P53		output

MD0

(P30)

MD1

(P31)

MD2 (P32)

MD3 (P33)

12

Image 12

NEC PD75P308 user manual Program Memory Write Procedure, VDD+1

Contents

Features DescriptionOrdering Information Quality Grade PIN Configuration ΜPD75P308 Block Diagram Contents Port Pins PIN Functions NON Port Pins Schmitt trigger input with hysteresis characteristics PIN INPUT/OUTPUT CircuitsInput buffer of Cmos standard COM Type F-BIN/OUT SEG Connect capacitor between VDD and P00/INT4, Reset pin Type M-C Differences Between μPD75P308 and μPD75308 Eprom Program memory address 0 clear mode +12.5 Write mode Verify mode Program inhibit mode Or HWriting and Verifying Prom Program Memory Operation Modes for WRITING/VERIFYING Program Memory Program Memory Write Procedure VDD+1 Program Memory Read Procedure Erasure μPD75P308K only Electrical Specifications Absolute Maximum Ratings Ta = 25C Main System Clock Oscillator Circuit Characteristics Ta = -10 to +70C, VDD = 5 to ±5Recommended Oscillation Circuit Constants Main System Clock Ceramic Oscillator Ta = -10 to +70C Capacitance Ta = 25C, VDD = 0 DC Characteristics Ta = -10 to +70C, VDD = 5V ±5% AC Characteristics Ta = -10 to + 70C, VDD = 5V ±5% Interrupt mode register IM0Operation Other Than Serial Transfer Serial Transfer Operation SBI Mode SCK internal clock output master SBI Mode SCK external clock output master AC Timing Test Point excluding X1 and XT1 inputs Clock TimingTI0 Timing Serial Transfer Timing THREE-LINE Serial I/O Mode TWO-LINE Serial I/O Mode Serial Transfer Timing BUS Release Signal Transfer Command Signal TransferReset Input Timing Interrupt Input Timing Data Retention Timing releasing Stop mode by Reset Ta = -10 to +70CBTM3 BTM2 BTM1 BTM0 Other than X1 or Program Memory Write Timing Program Memory Read TimingMD0 MD1 Package Drawings PIN Plastic QFP 14×20 PIN Ceramic Wqfn Millimeters Inches Recommended Soldering Conditions ΜPD75P308GF-3B9 80-pin plastic QFP 14 x 20 mmVPS Appendix A. Development Tools Prom writing tools Appendix B. Related Documents Processing of Unused Pins Cmos Devices only Static Electricity ALL MOS DevicesStatus Before Initialization ALL MOS Devices Fix the input level of Cmos devices Memo