NEC PD75P308 SBI Mode SCK internal clock output master, SBI Mode SCK external clock output master

μPD75P308

SBI MODE (SCK: internal clock output (master))

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

1600

ns

SCK

Cycle Time

tKCY3

tKL3

tKCY/2

SCK

High-, Low-Level

ns

Widths

tKH3

-50

SB0, 1 Set-Up Time (vs.

− )

tSIK3

SCK

150

ns

SB0, 1 Hold Time (vs.

− )

tKSI3

SCK

tKCY/2

ns

↓ → SB0, 1 Output

SCK

tKSO3

RL = 1kΩ, CL = 100pF*

0

250

ns

Delay Time

− →

↓

tKSB

SCK

tKCY

ns

SB0, 1

SB0, 1

↓ →

↓

tSBK

tKCY

ns

SCK

SB0, 1 Low-Level Width

tSBL

tKCY

ns

SB0, 1 High-Level Width

tSBH

tKCY

ns

*: RL and CL are load resistance and load capacitance of the SO output line.

SBI MODE (SCK: external clock output (master))

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

1600

ns

SCK

Cycle Time

tKCY4

tKL4

SCK High-, Low-Level

400

ns

Widths

tKH4

SB0, 1 Set-Up Time (vs.

− )

tSIK4

SCK

100

ns

SB0, 1 Hold Time (vs.

− )

tKSI4

SCK

tKCY/2

ns

↓ → SB0, 1 Output

SCK

tKSO4

RL = 1kΩ, CL = 100pF*

0

300

ns

Delay Time

− →

↓

tKSB

SCK

tKCY

ns

SB0, 1

SB0, 1 ↓ →

↓

tSBK

tKCY

ns

SCK

SB0, 1 Low-Level Width

tSBL

tKCY

ns

SB0, 1 High-Level Width

tSBH

tKCY

ns

*: RL and CL are load resistance and load capacitance of the SO output line.

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