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NEC PD75P308 user manual Connect capacitor between VDD and P00/INT4, Reset pin, Type M-C

Models: PD75P308

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		μPD75P308
TYPE M-C
		VDD
		P.U.R.
	P.U.R.	P–ch
	enable	P–ch
	enable
		IN/OUT
data	N-ch
	N-ch
output
disable
	P.U.R. : Pull–Up Resistor

1.4NOTES ON USING P00/INT4 AND RESET PINS

In addition to the functions shown in sections 1.1 and 1.2, the P00/INT4 and RESET pins also have a function to set a test mode (for IC testing) in which the internal operations of the μPD75P308 are tested.

When a voltage higher than VDD is applied to either of these pins, the test mode is set. This means that, even during ordinary operation, the μPD75P308 may be set in the test mode if a noise exceeding VDD is applied.

For example, if the wiring length of the P00/INT4 or RESET pin is too long, noise superimposed on the wiring line of the pin may cause the above problem.

Therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components.

•Connect diode with low VF between VDD and P00/INT4, RESET pin

V DD

Diode with		V DD
Diode with		V DD
low V F

•Connect capacitor between VDD and P00/INT4, RESET pin

V DD

V DD

P00/INT4, RESET

P00/INT4, RESET

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NEC PD75P308 user manual Connect capacitor between VDD and P00/INT4, Reset pin, Type M-C

Contents

Description FeaturesOrdering Information Quality GradeΜPD75P308 PIN ConfigurationBlock Diagram Contents PIN Functions Port PinsNON Port Pins Schmitt trigger input with hysteresis characteristics PIN INPUT/OUTPUT CircuitsInput buffer of Cmos standard COM Type F-BIN/OUT SEG Type M-C Connect capacitor between VDD and P00/INT4, Reset pinEprom Differences Between μPD75P308 and μPD75308+12.5 Write mode Verify mode Program inhibit mode Or H Program memory address 0 clear modeWriting and Verifying Prom Program Memory Operation Modes for WRITING/VERIFYING Program MemoryVDD+1 Program Memory Write ProcedureProgram Memory Read Procedure Erasure μPD75P308K only Absolute Maximum Ratings Ta = 25C Electrical SpecificationsTa = -10 to +70C, VDD = 5 to ±5 Main System Clock Oscillator Circuit CharacteristicsRecommended Oscillation Circuit Constants Main System Clock Ceramic Oscillator Ta = -10 to +70CCapacitance Ta = 25C, VDD = 0 DC Characteristics Ta = -10 to +70C, VDD = 5V ±5% AC Characteristics Ta = -10 to + 70C, VDD = 5V ±5% Interrupt mode register IM0Operation Other Than Serial Transfer Serial Transfer Operation SBI Mode SCK external clock output master SBI Mode SCK internal clock output masterAC Timing Test Point excluding X1 and XT1 inputs Clock TimingTI0 Timing TWO-LINE Serial I/O Mode Serial Transfer Timing THREE-LINE Serial I/O ModeCommand Signal Transfer Serial Transfer Timing BUS Release Signal TransferReset Input Timing Interrupt Input TimingData Retention Timing releasing Stop mode by Reset Ta = -10 to +70CBTM3 BTM2 BTM1 BTM0 Other than X1 or Program Memory Write Timing Program Memory Read TimingMD0 MD1 PIN Plastic QFP 14×20 Package DrawingsMillimeters Inches PIN Ceramic WqfnRecommended Soldering Conditions ΜPD75P308GF-3B9 80-pin plastic QFP 14 x 20 mmVPS Prom writing tools Appendix A. Development ToolsAppendix B. Related Documents Static Electricity ALL MOS Devices Processing of Unused Pins Cmos Devices onlyStatus Before Initialization ALL MOS Devices Fix the input level of Cmos devicesMemo