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NEC PD75P308 user manual Ta = -10 to +70C, Data Retention Timing releasing Stop mode by Reset

Models: PD75P308

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μPD75P308

LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE

(Ta = -10 to +70°C)

Parameter	Symbol		Conditions		MIN.	TYP.	MAX.	Unit

Data Retention Supply	VDDDR				2.0		6.0	V
Voltage	VDDDR				2.0		6.0	V
Voltage

Data Retention Supply	IDDDR	VDDDR = 2.0V				0.1	10	μA
Current*1	IDDDR	VDDDR = 2.0V				0.1	10	μA
Current*1

Release Signal Set Time	SREL				0			μs
Release Signal Set Time	t
Oscillation Stabilization						217/fX		ms
Oscillation Stabilization	tWAIT	Released by RESET				217/fX		ms
Wait Time*2
		Released by interrupt				*3		ms
		Released by interrupt				*3		ms

*1: Does not include current folowing through internal pull-up resistor

2:The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable operation when oscillation is started.

3:Depends on the setting of the basic interval timer mode register (BTM) as follows:

BTM3	BTM2	BTM1	BTM0	WAIT time ( ): fX = 4.19 MHz
—	0	0	—	220/fX (approx. 250 ms)
—	0	1	—	217/fX (approx. 31.3 ms)
—	1	0	—	215/fX (approx. 7.82 ms)
—	1	1	—	213/fX (approx. 1.95 ms)

DATA RETENTION TIMING (releasing STOP mode by RESET)

Internal reset operation

HALT mode

STOP mode

Data retention mode

VDD

VDDDR

tSREL

STOP instruction execution

Operation mode

RESET

tWAIT

DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)

HALT mode

STOP mode

Data retention mode

VDD

VDDDR

tSREL

STOP instruction execution

Standby release signal (interrupt request)

Operation mode

tWAIT	25

Image 25

NEC PD75P308 user manual Ta = -10 to +70C, Data Retention Timing releasing Stop mode by Reset, BTM3 BTM2 BTM1 BTM0

Contents

Description FeaturesOrdering Information Quality GradeΜPD75P308 PIN ConfigurationBlock Diagram Contents PIN Functions Port PinsNON Port Pins PIN INPUT/OUTPUT Circuits Schmitt trigger input with hysteresis characteristicsInput buffer of Cmos standard Type F-B COMIN/OUT SEG Type M-C Connect capacitor between VDD and P00/INT4, Reset pinEprom Differences Between μPD75P308 and μPD75308+12.5 Write mode Verify mode Program inhibit mode Or H Program memory address 0 clear modeWriting and Verifying Prom Program Memory Operation Modes for WRITING/VERIFYING Program MemoryVDD+1 Program Memory Write ProcedureProgram Memory Read Procedure Erasure μPD75P308K only Absolute Maximum Ratings Ta = 25C Electrical SpecificationsTa = -10 to +70C, VDD = 5 to ±5 Main System Clock Oscillator Circuit CharacteristicsRecommended Oscillation Circuit Constants Main System Clock Ceramic Oscillator Ta = -10 to +70CCapacitance Ta = 25C, VDD = 0 DC Characteristics Ta = -10 to +70C, VDD = 5V ±5% Interrupt mode register IM0 AC Characteristics Ta = -10 to + 70C, VDD = 5V ±5%Operation Other Than Serial Transfer Serial Transfer Operation SBI Mode SCK external clock output master SBI Mode SCK internal clock output masterClock Timing AC Timing Test Point excluding X1 and XT1 inputsTI0 Timing TWO-LINE Serial I/O Mode Serial Transfer Timing THREE-LINE Serial I/O ModeCommand Signal Transfer Serial Transfer Timing BUS Release Signal TransferReset Input Timing Interrupt Input TimingTa = -10 to +70C Data Retention Timing releasing Stop mode by ResetBTM3 BTM2 BTM1 BTM0 Other than X1 or Program Memory Read Timing Program Memory Write TimingMD0 MD1 PIN Plastic QFP 14×20 Package DrawingsMillimeters Inches PIN Ceramic WqfnΜPD75P308GF-3B9 80-pin plastic QFP 14 x 20 mm Recommended Soldering ConditionsVPS Prom writing tools Appendix A. Development ToolsAppendix B. Related Documents Static Electricity ALL MOS Devices Processing of Unused Pins Cmos Devices onlyStatus Before Initialization ALL MOS Devices Fix the input level of Cmos devicesMemo