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NEC PD75P308 user manual Package Drawings, PIN Plastic QFP 14×20

Models: PD75P308

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μPD75P308

5.PACKAGE DRAWINGS

80 PIN PLASTIC QFP (14×20)

F

	A
	B
64	41
65	40

			80																										25
			1																										24

detail of lead end

C

D

S

Q

5°±5°

G

P

H I M

N

J

K

L

M

P80GF-80-3B9-2

NOTE

Each lead centerline is located within 0.15

mm(0.006 inch) of its true position (T.P.) at maximum material condition.

ITEM	MILLIMETERS	INCHES

A	23.6±0.4	0.929±0.016

B	20.0±0.2	0.795+0.009–0.008
C	14.0±0.2	0.551+0–0..008009

D	17.6±0.4	0.693±0.016

F	1.0	0.039

G	0.8	0.031

H	0.35±0.10	0.014+0.004–0.005
I	0.15	0.006

J	0.8 (T.P.)	0.031 (T.P.)

K	1.8±0.2	0.071+0.008–0.009

L	0.8±0.2	0.031+0.009–0.008

M	0.15+0.10–0.05	0.006+0.004–0.003
N	0.15	0.006

P	2.7	0.106

Q	0.1±0.1	0.004±0.004

S	3.0 MAX.	0.119 MAX.

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Image 28

NEC PD75P308 user manual Package Drawings, PIN Plastic QFP 14×20

Contents

Features DescriptionOrdering Information Quality GradePIN Configuration ΜPD75P308Block Diagram Contents Port Pins PIN FunctionsNON Port Pins PIN INPUT/OUTPUT Circuits Schmitt trigger input with hysteresis characteristicsInput buffer of Cmos standard Type F-B COMIN/OUT SEG Connect capacitor between VDD and P00/INT4, Reset pin Type M-CDifferences Between μPD75P308 and μPD75308 EpromProgram memory address 0 clear mode +12.5 Write mode Verify mode Program inhibit mode Or HWriting and Verifying Prom Program Memory Operation Modes for WRITING/VERIFYING Program MemoryProgram Memory Write Procedure VDD+1Program Memory Read Procedure Erasure μPD75P308K only Electrical Specifications Absolute Maximum Ratings Ta = 25CMain System Clock Oscillator Circuit Characteristics Ta = -10 to +70C, VDD = 5 to ±5Recommended Oscillation Circuit Constants Main System Clock Ceramic Oscillator Ta = -10 to +70CCapacitance Ta = 25C, VDD = 0 DC Characteristics Ta = -10 to +70C, VDD = 5V ±5% Interrupt mode register IM0 AC Characteristics Ta = -10 to + 70C, VDD = 5V ±5%Operation Other Than Serial Transfer Serial Transfer Operation SBI Mode SCK internal clock output master SBI Mode SCK external clock output masterClock Timing AC Timing Test Point excluding X1 and XT1 inputsTI0 Timing Serial Transfer Timing THREE-LINE Serial I/O Mode TWO-LINE Serial I/O ModeSerial Transfer Timing BUS Release Signal Transfer Command Signal TransferReset Input Timing Interrupt Input TimingTa = -10 to +70C Data Retention Timing releasing Stop mode by ResetBTM3 BTM2 BTM1 BTM0 Other than X1 or Program Memory Read Timing Program Memory Write TimingMD0 MD1 Package Drawings PIN Plastic QFP 14×20PIN Ceramic Wqfn Millimeters InchesΜPD75P308GF-3B9 80-pin plastic QFP 14 x 20 mm Recommended Soldering ConditionsVPS Appendix A. Development Tools Prom writing toolsAppendix B. Related Documents Processing of Unused Pins Cmos Devices only Static Electricity ALL MOS DevicesStatus Before Initialization ALL MOS Devices Fix the input level of Cmos devicesMemo