Block Diagram | NEC PD75P308 specs

BASIC

INTERVAL

TIMER

INTBT

TI0/P13 TIMER/EVENT

PTO0/P20 COUNTER #0

		INTT0
	BUZ/P23	WATCH
	BUZ/P23	TIMER
		TIMER

		PORT0
PROGRAM	SP(8)	PORT1
COUNTER(13)	SP(8)
COUNTER(13)	CY
	CY
	ALU	PORT2
		PORT2
	BANK	PORT3
		PORT3
		PORT4
PROGRAM
MEMORY	GENERAL REG.	PORT5

4P00-P03

4P10-P13

4 P20-P23

4P30-P33 /MD0-MD3

4P40-P43

4P50-P53

BLOCK DIAGRAM

SI/SBI/P03

SO/SB0/P02

SCK/P01

INTW fLCD

SERIAL

INTERFACE

INTCSI

	(PROM)
	DECODE		PORT6

	AND	DATA
			PORT7
	CONTROL
		MEMORY
	8064 x 8 BITS
		(RAM)

		512 x 4 BITS

4P60-P63

4P70-P73

24 S0-S23

INT0/P10

INT1/P11

INT2/P12

INT4/P00

KR0/P60- KR3/P63, KR4/P70- KR7/P73

8

INTERRUPT

CONTROL

BIT SEQ.

BUFFER(16)

LCD

CONTROLLER

/DRIVER

fX/2 N

	CLOCK		SYSTEM CLOCK
		CLOCK	GENERATOR		STAND BY	CPU	fLCD
	OUTPUT
		DIVIDER			CONTROL	CLOCK
	CONTROL		SUB
				MAIN
	PCL/P22		XT1 XT2	X1	X2	VPP VDD VSS	RESET

8S24/BP0 -S31/BP7

4 COM0-COM3

3VLCO -VLC2

BIAS

LCDCL/P30

SYNC/P30

μPD75P308

3

Image 3

NEC PD75P308 user manual Block Diagram

Contents

Quality Grade FeaturesDescription Ordering Information ΜPD75P308 PIN Configuration Block Diagram Contents PIN Functions Port Pins NON Port Pins Schmitt trigger input with hysteresis characteristics PIN INPUT/OUTPUT CircuitsInput buffer of Cmos standard COM Type F-BIN/OUT SEG Type M-C Connect capacitor between VDD and P00/INT4, Reset pin Eprom Differences Between μPD75P308 and μPD75308 Operation Modes for WRITING/VERIFYING Program Memory Program memory address 0 clear mode+12.5 Write mode Verify mode Program inhibit mode Or H Writing and Verifying Prom Program Memory VDD+1 Program Memory Write Procedure Program Memory Read Procedure Erasure μPD75P308K only Absolute Maximum Ratings Ta = 25C Electrical Specifications Main System Clock Ceramic Oscillator Ta = -10 to +70C Main System Clock Oscillator Circuit CharacteristicsTa = -10 to +70C, VDD = 5 to ±5 Recommended Oscillation Circuit Constants Capacitance Ta = 25C, VDD = 0 DC Characteristics Ta = -10 to +70C, VDD = 5V ±5% AC Characteristics Ta = -10 to + 70C, VDD = 5V ±5% Interrupt mode register IM0Operation Other Than Serial Transfer Serial Transfer Operation SBI Mode SCK external clock output master SBI Mode SCK internal clock output master AC Timing Test Point excluding X1 and XT1 inputs Clock TimingTI0 Timing TWO-LINE Serial I/O Mode Serial Transfer Timing THREE-LINE Serial I/O Mode Interrupt Input Timing Serial Transfer Timing BUS Release Signal TransferCommand Signal Transfer Reset Input Timing Data Retention Timing releasing Stop mode by Reset Ta = -10 to +70CBTM3 BTM2 BTM1 BTM0 Other than X1 or Program Memory Write Timing Program Memory Read TimingMD0 MD1 PIN Plastic QFP 14×20 Package Drawings Millimeters Inches PIN Ceramic Wqfn Recommended Soldering Conditions ΜPD75P308GF-3B9 80-pin plastic QFP 14 x 20 mmVPS Prom writing tools Appendix A. Development Tools Appendix B. Related Documents Fix the input level of Cmos devices Processing of Unused Pins Cmos Devices onlyStatic Electricity ALL MOS Devices Status Before Initialization ALL MOS Devices Memo