ΜPD75P308, PIN Configuration | NEC specification

μPD75P308

PIN CONFIGURATION

S12 1

S13 2

S14 3

S15 4

S16 5

S17 6

S18 7

S19 8

S20 9

S21 10

S22 11

S23 12

S24/BP0 13

S25/BP1 14

S26/BP2 15

S27/BP3 16

S28/BP4 17

S29/BP5 18

S30/BP6 19

S31/BP7 20

COM0 21

COM1 22

COM2 23

COM3 24

S11	S10	S9	S8	S7	S6	S5	S4	S3	S2	S1	S0	RESET	P73/KR7	P72/KR6	P71/KR5
80 79 78 77 76					75 74 73 72 71 70 69 68								67 66 65
															64
															63
															62
															61
															60
															59
															58
															57
							μPD75P308K	PD75P308GFμ							56
							μPD75P308K	PD75P308GFμ							52
															55
															54
															53
								-
								3B9							51
															51

50

49

48

47

46

45

44

43

42

41

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

P70/KR4

P63/KR3

P62/KR2

P61/KR1

P60/KR0

X2

X1

VPP

XT2

XT1

VDD

P33 (MD3)

P32 (MD2) P31/SYNC (MD1) P30/LCDCL (MD0) P23/BUS P22/PCL

P21

P20/PTO0

P13/TI0

P12/INT2

P11/INT1

P10/INT0

P03/SI/SBI

BIAS

VLCO

VLC1

VLC2

P40

P41

P42

P43

V

P50

P51

P52

P53

P00/INT4

SS

P01/SCK

P02/SO/SB0

2

Image 2

NEC user manual ΜPD75P308, PIN Configuration

Contents

Ordering Information FeaturesDescription Quality Grade PIN Configuration ΜPD75P308 Block Diagram Contents Port Pins PIN Functions NON Port Pins Input buffer of Cmos standard Schmitt trigger input with hysteresis characteristicsPIN INPUT/OUTPUT Circuits IN/OUT SEG COMType F-B Connect capacitor between VDD and P00/INT4, Reset pin Type M-C Differences Between μPD75P308 and μPD75308 Eprom Writing and Verifying Prom Program Memory Program memory address 0 clear mode+12.5 Write mode Verify mode Program inhibit mode Or H Operation Modes for WRITING/VERIFYING Program Memory Program Memory Write Procedure VDD+1 Program Memory Read Procedure Erasure μPD75P308K only Electrical Specifications Absolute Maximum Ratings Ta = 25C Recommended Oscillation Circuit Constants Main System Clock Oscillator Circuit CharacteristicsTa = -10 to +70C, VDD = 5 to ±5 Main System Clock Ceramic Oscillator Ta = -10 to +70C Capacitance Ta = 25C, VDD = 0 DC Characteristics Ta = -10 to +70C, VDD = 5V ±5% Operation Other Than Serial Transfer AC Characteristics Ta = -10 to + 70C, VDD = 5V ±5%Interrupt mode register IM0 Serial Transfer Operation SBI Mode SCK internal clock output master SBI Mode SCK external clock output master TI0 Timing AC Timing Test Point excluding X1 and XT1 inputsClock Timing Serial Transfer Timing THREE-LINE Serial I/O Mode TWO-LINE Serial I/O Mode Reset Input Timing Serial Transfer Timing BUS Release Signal TransferCommand Signal Transfer Interrupt Input Timing BTM3 BTM2 BTM1 BTM0 Data Retention Timing releasing Stop mode by ResetTa = -10 to +70C Other than X1 or MD0 MD1 Program Memory Write TimingProgram Memory Read Timing Package Drawings PIN Plastic QFP 14×20 PIN Ceramic Wqfn Millimeters Inches VPS Recommended Soldering ConditionsΜPD75P308GF-3B9 80-pin plastic QFP 14 x 20 mm Appendix A. Development Tools Prom writing tools Appendix B. Related Documents Status Before Initialization ALL MOS Devices Processing of Unused Pins Cmos Devices onlyStatic Electricity ALL MOS Devices Fix the input level of Cmos devices Memo