4. Configuration Options

Table 4-13. CSU/DSU Data Port Physical Interface Options (2 of 2)

Transmit Clock Source

Possible Settings: Internal, External

Default Setting: Internal

Determines whether the DTE’s transmitted data is clocked into the FrameSaver unit by internal transmit clock or external clock provided by the DTE.

NOTE: Changing this setting causes the FrameSaver unit to abort any physical port tests, including any DTE-initiated loopback tests.

Internal – The FrameSaver unit uses its own internal clock, the interchange circuit DB (ITU 114) – Transmit Signal Element Timing (TXC) (DCE source), for timing the incoming data.

External – The DTE provides the clock for the transmitted data, and the FrameSaver unit uses the interchange circuit DA (ITU 113) – Transmit Signal Element Timing (XTXC) (DTE source) for timing the incoming data.

Monitor RTS (Control)

Possible Settings: Enable, Disable

Default Setting: Enable

Specifies if the state of the Request To Send (RTS) circuits on the user data port are used to determine when valid data communication with the DTE is possible. When the RTS off condition is detected, CTS is deasserted, LMI is declared down, and no further transfer of frame relay data can occur on this interface.

Enable – Interchange circuit CA (ITU 105) – RTS is monitored to determine when valid DTE data communication is possible.

Disable – RTS is not monitored. RTS is assumed to be asserted and data is being transmitted, regardless of the state of the lead.

Monitor DTR

Possible Settings: Enable, Disable

Default Setting: Enable

Specifies whether the state of the DTE Ready (DTR) circuit on the user data port used to determine when valid data communication is possible with the DTE. When the DTR off condition is detected, an alarm is generated, LMI is declared down, and no further transfer of frame relay data can occur on this interface.

Enable – Interchange circuit CD (ITU 108/1/2) – DTR is monitored to determine when valid data is sent from the DTE.

Disable – DTR is not monitored. DTR is assumed to be asserted and data is being transmitted, regardless of the state of the lead.

Port (DTE) Initiated Loopbacks

Possible Settings: Local, Disable

Default Setting: Disable

Allows a local external DTE Loopback to be started or stopped via the port’s attached DTE interchange lead LL (ITU 141).

Local – The DTE attached to the port controls the local external DTE Loopback.

Disable – The DTE attached to the port cannot control the local external DTE Loopback.

9700-A2-GB20-20

December 2002

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Paradyne 9720 CSU/DSU Data Port Physical Interface Options 2, Transmit Clock Source, Monitor RTS Control, Monitor DTR

9720, 9788 specifications

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