S3C8245/P8245/C8249/P8249 INTERRUPT STRUCTURE
5-5
Table 5-1. Interrupt Vectors
Vector Address Interrupt Source Request Reset/Clear
Decimal
Value Hex
Value Interrupt
Level Priority in
Level H/W S/W
256 100H Basic timer overflow Reset –√
226 E2HTimer A overflow IRQ0 0√ √
224 E0HTimer A match/capture 1√ √
228 E4HTimer B match IRQ1 –√
230 E6HTimer 0 match IRQ2 –√ √
234 EAH Timer 1 overflow IRQ3 0 √ √
232 E8H Timer 1 match/capture 1√ √
236 ECH SIO interrupt IRQ4 –√
238 EEH Watch timer overflow IRQ5 –√
246 F6H P0.3 external interrupt IRQ6 3 √
244 F4H P0.2 external interrupt 2√
242 F2H P0.1 external interrupt 1√
240 F0H P0.0 external interrupt 0√
254 FEH P0.7 external interrupt IRQ7 3√
252 FCH P0.6 external interrupt 2√
250 FAH P0.5 external interrupt 1√
248 F8H P0.4 external interrupt 0√
NOTES:
1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on.
2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority
over one with a higher vector address. The priorities within a given level are fixed in hardware.
3. Timer A or Timer 1 can not service two interrupt sources simultaneously, then only one interrupt source have to be
used.