Samsung C8249, P8245, P8249, S3C8245 - page 236

S3C8245/P8245/C8249/P8249 I/O PORTS
9-3
PORT 0
Port 0 is an 8-bit I/O Port that you can use two ways:
—General-purpose I/O
—External interrupt inputs for INT0–INT7
Port 0 is accessed directly by writing or reading the port 0 data register, P0 at location F6H in set 1, bank 0.
Port 0 Control Register (P0CONH, P0CONL)
Port 0 pins are configured individually by bit-pair settings in two control registers located in set 1, bank 0:
P0CONL (low byte, E1H) and P0CONH (high byte, E0H).
When you select output mode, a push-pull circuit is automatically configured. In input mode, three different
selections are available:
—Schmitt trigger input with interrupt generation on falling signal edges.
—Schmitt trigger input with interrupt generation on rising signal edges.
—Schmitt trigger input with interrupt generation on falling/rising signal edges.
Port 0 Interrupt Enable and Pending Registers (P0INT, P0PND)
To process external interrupts at the port 0 pins, two additional control registers are provided: the port 0 interrupt
enable register P0INT (E2H, set 1, bank 0) and the port 0 interrupt pending register P0PND (E3H, set 1, bank 0).
The port 0 interrupt pending register P0PND lets you check for interrupt pending conditions and clear the pending
condition when the interrupt service routine has been initiated. The application program detects interrupt requests by
polling the P0PND register at regular intervals.
When the interrupt enable bit of any port 0 pin is “1”, a rising or falling signal edge at that pin will generate an
interrupt request. The corresponding P0PND bit is then automatically set to “1” and the IRQ level goes low to signal
the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software
must the clear the pending condition by writing a “0” to the corresponding P0PND bit.