Samsung C8249, P8245, P8249, S3C8245 Figure 12-2. Timer 0 Functional Block Diagram

S3C8245/P8245/C8249/P8249 16-BIT TIMER 0/1
12-3
BLOCK DIAGRAM
Timer 0 Data H/L Reg
(Read/Write)
Timer 0 Buffer Reg
16-bit Comparator
16-bit up-Counter H/L
(Read Only)
Match
Bit 3
T0INT
Counter clear signal (T0CON.3)
Bits 7, 6, 5
M
U
X
fxx/256
fxx/64
fxx/8
fxx/1
TBOF
Bit 2
Clear
Bit 0
Bit 1
IRQ2
Pending
R
Data Bus
8
Data Bus
8
NOTES:
1. To be loaded T0DATA value to buffer register for comparing, T0CON.3 bit must be set 1.
2. Timer 0 input clock must be slower than CPU clock.
Figure 12-2. Timer 0 Functional Block Diagram